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STRF6624 Datasheet(PDF) 9 Page - Allegro MicroSystems |
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STRF6624 Datasheet(HTML) 9 Page - Allegro MicroSystems |
9 / 16 page Series STR-F6600 OFF-LINE QUASI-RESONANT FLYBACK SWITCHING REGULATORS 9 Functional Description and Operation (cont’d) The voltage V OCP (pin 1) has the same form as the VDS waveform. The condition for quasi-resonant operation is given by: 2.0 V < V OCP > 5.5 V for >1 µs Transformer design is exactly as for any other discon- tinuous-mode type flyback. For optimum EMI/efficiency performance, quasi- resonance turn off is achieved when the MOSFET is at zero voltage and zero current; that is, at one half cycle of the quasi-resonance frequency, fr. Over-Current Protection (OCP) Functions Refer to the Functional Block diagram and Typical Application diagram (figure 6). The regulator implements pulse-by-pulse over-current protection, which limits the maximum drain current in the MOSFET on every pulse by switching off the internal drive to the MOSFET, and the MOSFET drain current is detected across R5. Drive Circuit Refer to the Functional Block Diagram. This circuit is driven from the oscillator and provides the current drive to charge and discharge the MOSFET gate-source capacitance, thereby switching the device on and off. The basic circuit configuration is totem-pole type with an additional limiting resistor in the gate circuit at turn on. This limits the turn on speed of the MOSFET, thereby reducing EMI due to the discharge of primary capacitance. This is possible because of the low-voltage switching, zero-current switching nature of the turn on. The value of the turn-off resistance is lower, allowing the device turn-off current to be increased. This reduces the turn-off loss in the MOSFET. The gate drive voltage (8.3 V) is such that even with 0.73 V across R5 (drain current sense resistor), the MOSFET is fully enhanced, allowing full use to be made of its high current handling capacity. Latch Circuit The latch circuit keeps the oscillator output low to inhibit operation of the regulator when over-voltage protection (OVP) and thermal shutdown (TSD) circuits are in operation. As long as the latch hold-in current is 400 µA (max., supplied via R S) with VIN at 8.5 V (pin 4), the regulator will stay in the off state. An internal noise filter provides 10 µs of noise immu- nity to prevent spurious operation of the over-voltage protection or thermal shutdown. With the latch ‘on’, the voltage on pin 4 cycles between 16 V and 10 V as shown in figure 9. This is due to the higher current drawn when the pin 4 is at 16 V compared to that drawn close to shutdown (10 V). Pulling V IN (pin 4) below 6.5 V will reset the latch circuit, re-enabling the regulator. Thermal Shutdown This internal feature triggers the latch if the internal frame temperature exceeds 140 °C (typ.). The temperature is sensed on the control IC, but also protects against overheating of the MOSFET as the MOSFET and the control IC are mounted on the same lead frame. Additionally, protection is provided for other on- board components. VIN TIME 16 V (TYP.) 10 V (TYP.) Figure 9 – Example of V IN Terminal Voltage Waveform at Latch Circuit On |
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