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TMP451-Q1

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SLOS877B – OCTOBER 2014 – REVISED JUNE 2019

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Programming (continued)

7.5.1.3 Serial Bus Address

To communicate with the TMP451-Q1 device, the master must first address slave devices using a slave address

byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing

a read or write operation. The TMP451-Q1 SMBus addresses are shown in Table 3. Additional factory-

programmed device addresses are available upon request.

Table 3. TMP451-Q1 SMBus Addresses

Orderable Part Number (DQF Package)

SMBus Address (7-bit)

TMP451HQDQFRQ1

49

TMP451AQDQFRQ1

4C

TMP451JQDQFRQ1

4E

7.5.1.4 Read and Write Operations

Accessing a particular register on the TMP451-Q1 device is accomplished by writing the appropriate value to the

pointer register. The value for the pointer register is the first byte transferred after the slave address byte with the

R/W bit low. Every write operation to the TMP451-Q1 device requires a value for the pointer register (see

Figure 15).

When reading from the TMP451-Q1 device the last value stored in the pointer register by a write operation is

used to determine which register is read by a read operation. To change which register is read for a read

operation, a new value must be written to the pointer register. This transaction is accomplished by issuing a

slave address byte with the R/W bit low, followed by the pointer register byte; no additional data are required.

The master can then generate a start condition and send the slave address byte with the R/W bit high to initiate

the read command; see Figure 16 for details of this sequence.

If repeated reads from the same register are desired, it is not necessary to continually send the pointer register

bytes, because the TMP451-Q1 retains the pointer register value until it is changed by the next write operation.

The register bytes are sent MSB first, followed by the LSB.

Read operations should be terminated by issuing a not-acknowledge command at the end of the last byte to be

read. For single-byte operation, the master must leave the SDA line high during the acknowledge time of the first

byte that is read from the slave.

7.5.1.5 Timeout Function

If the SMBus timeout function is enabled, the TMP451-Q1 device resets the serial interface if either SCL or SDA

are held low for 25 ms (typical) between a start and stop condition. If the TMP451-Q1 device is holding the bus

low, the device releases the bus and waits for a start condition. To avoid activating the timeout function,

maintaining a communication speed of at least 1 kHz for the SCL operating frequency is necessary. The SMBTO

bit (bit 7) of the consecutive ALERT register controls the timeout enable. Setting the SMBTO bit to a value of 0

(default) disables the timeout. Setting the SMBTO bit to a value of 1 enables the function.

7.5.1.6 High-speed Mode

For the two-wire bus to operate at frequencies above 1 MHz, the master device must issue a high-speed mode

(Hs-mode) master code (0000 1xxx) as the first byte after a start condition to switch the bus to high-speed

operation. The TMP451-Q1 device does not acknowledge this byte, but switches the input filters on SDA and

SCL and the output filter on SDA to operate in HS-mode, allowing transfers at up to 2.5 MHz. After the Hs-mode

master code has been issued, the master transmits a two-wire slave address to initiate a data transfer operation.

The bus continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the stop

condition, the TMP451-Q1 device switches the input and output filters back to fast mode operation.