RTL8101L
2003-05-28
Rev.1.3
55
10. Functional Description
10.1 Transmit operation
The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. When the
entire packet has been transferred to the Tx buffer, the RTL8101L is instructed to move the data from the Tx buffer to the
internal transmit FIFO in PCI bus master mode. When the transmit FIFO contains a complete packet or is filled to the
programmed threshold level, the RTL8101L begins packet transmission.
10.2 Receive operation
The incoming packet is placed in the RTL8101L's Rx FIFO. Concurrently, the RTL8101L performs address filtering of
multicast packets according to its hash algorithms. When the amount of data in the Rx FIFO reaches the level defined in the
Receive Configuration Register, the RTL8101L requests the PCI bus to begin transferring the data to the Rx buffer in PCI
bus master mode.
10.3 Wander Compensation
The 8101L is ANSI TP-PMD compliant and supports input and Base Line Wander (BLW) compensation in 100Base-TX mode.
The 8101L does not require external attenuation circuitry at its receive inputs, RD+/-. It accepts TP-PMD compliant waveforms
directly, requiring only a 100Ω termination and a 1:1 transformer.
BLW is the change in the average DC content, over time, of an AC coupled digital transmission over a given transmission medium.
BLW is a result from the interaction between the low frequency components of a transmitted bit stream and the frequency response
of the AC coupling component(s) within the transmission system. If the low frequency content of the digital bit stream goes below
the low frequency pole of the AC coupling transformers, then the droop characteristics of the transformers will dominate resulting
in potentially serious BLW. If BLW is not compensated, packet loss can occur.
10.4 Signal Detect
The 8101L supports signal detect in 100Base-TX mode. Therefore, the reception of normal 10Base-T link pulses and fast link
pulses defined by IEEE 802.3u Auto-negotiation by the 100Base-TX receiver do not cause the 8101L to assert signal detect.
The signal detect function of the 8101L is incorporated to meet the specifications mandated by the ANSI FDDI TP-PMD standard
as well as the IEEE 802.3 100Base-TX standard for both voltage thresholds and timing parameters.
10.5 Line Quality Monitor
The line quality monitor function is available in 100Base-TX mode. It is possible to determine the amount of Equalization being
used by accessing certain test registers with the DSP engine. This provides a crude indication of connected cable length. This
function allows for a quick and simple verification of the line quality in that any significant deviation from an expected register
value (based on a known cable length) would indicate that the signal quality has deviated from the expected nominal case.
10.6 Clock Recovery Module
The Clock Recovery Module (CRM) is supported in 100Base-TX mode. The CRM accepts 125Mb/s MLT3 data from the
equalizer. The DPLL locks onto the 125Mb/s data stream and extracts a 125MHz recovered clock. The extracted and
synchronized clock and data are used as required by the synchronous receive operations.
10.7 Loopback Operation
Loopback mode is normally used to verify that the logic operations up to the Ethernet cable function correctly. In loopback mode
for 100Mbps, the RTL8101L takes frames from the transmit descriptor and transmits them up to internal Twister logic.
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