RTL8101L
2003-05-28
Rev.1.3
49
10-1
-
Reserved (read back 0)
0
BROMEN
Boot ROM Enable: This is used by the PCI BIOS to enable accesses to Boot ROM.
ILR: Interrupt Line Register
The Interrupt Line Register is an 8-bit register used to communicate with the routing of the interrupt. It is written by the
POST software to set interrupt line for the RTL8101L.
IPR: Interrupt Pin Register
The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8101L. The RTL8101L uses
INTA interrupt pin. Read only. IPR = 01H.
MNGNT: Minimum Grant Timer: Read only
Specifies how long a burst period the RTL8101L needs at 33 MHz clock rate in units of 1/4 microsecond. This field
will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.
MXLAT: Maximum Latency Timer: Read only
Specifies how often the RTL8101L needs to gain access to the PCI bus in unit of 1/4 microsecond. This field will be
set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.
Cap_ID: Capability ID: Read only
Read as 01h (PCI bus power management capability ID)
Next_Item_Ptr: Next Item Pointer: Read only
Read as 00h (Last capability list)
Power Management Capabilities:
Bit
Type
Function
15
R
Read as 1 (PME# can be asserted from D3cold)
14
R
Read as 1 (PME# can be asserted from D3hot)
13
R
Read as 0 (PME# can not be asserted from D2)
12
R
Read as 0 (PME# can not be asserted from D1)
11
R
Read as 0 (PME# can not be asserted from D0)
10
R
Read as 0 (Not support D2 state)
9
R
Read as 0 (Not support D1 state)
8:6
R
Read as 010 (consume maximum 100mA from Vaux)
5
R
Read as 1 (Device Specific Initialization (DSI) required)
4
R
Read as 0
3
R
Read as 0 (PCI clock is not required for PME# operation)
2:0
R
Read as 010b
(PCI Power Management Interface Specification Revision 1.1)
Once Vaux is not supplied, bit[15] read as 0 to indicates PME# is not supported in D3(cold), and bit[8:6] read as 000b.
PMCSR:
Bit
Type
Function
15
R/W
PME_Status : 0 : Normal
1 : PME# asserted
14:13
R
Data_Scale: Read as 00b
12:9
R
Data_Select: Read as 0000b
8
R/W
PME_En : 0 : Disable
1 : Enable
7:2
R
Read as 0
1:0
R/W
PowerState : 00:D0 01:Reserved 10:Reserved 11:D3hot
Write a “1” to bit 15 will clear it and cause the function to stop asserting PME#. Write a “0” has no effect. Note that bit 15 is
independent of bit 8.
Write “01” and “10” to bit 1,0 has no effect to RTL8101L. RTL8101L terminate the cycle normally and discard the data (bit 1,0
only).
Bit 15 and bit 8 are sticky which means indeterminate after system reset. System OS should clear them after boot. These 2 bits
consume power from Vaux. Bits except bit 15/8 consume power from normal power source.
Because only PCI 2.2 support auxiliary power Vaux, chip designer must pay attention to the interface of PME# related circuit
and non-PME# related circuit.
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