RTL8101L
2003-05-28
Rev.1.3
48
Reads will return a 0, writes are ignored.
LTR: Latency Timer Register
Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8101L.
When the RTL8101L asserts FRAMEB, it enables its latency timer to count. If the RTL8101L deasserts FRAMEB prior
to count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the RTL8101L initiates
transaction termination as soon as its GNTB is deasserted. Software is able to read or write, and the default value is 00H.
HTR: Header Type Register
Reads will return a 0, writes are ignored.
BIST: Built-in Self Test
Reads will return a 0, writes are ignored.
IOAR: This register specifies the BASE IO address which is required to build an address map during configuration. It also
specifies the number of bytes required as well as an indication that it can be mapped into IO space.
Bit
Symbol
Description
31-8
IOAR31-8 BASE IO Address: This is set by software to the Base IO address for the operational register map.
7-2
IOSIZE
Size Indication: Read back as 0. This allows the PCI bridge to determine that the RTL8101L requires
256 bytes of IO space.
1
-
Reserved
0
IOIN
IO Space Indicator: Read only. Set to 1 by the RTL8101L to indicate that it is capable of being mapped
into IO space.
MEMAR: This register specifies the base memory address for memory accesses to the RTL8101L operational registers. This
register must be initialized prior to accessing any RTL8101L's register with memory access.
Bit
Symbol
Description
31-8
MEM31-8 Base Memory Address: This is set by software to the base address for the operational register map.
7-4
MEMSIZE Memory Size: These bits return 0, which indicates that the RTL8101L requires 256 bytes of Memory Space.
3
MEMPF
Memory Prefetchable: Read only. Set to 0 by the RTL8101L.
2-1
MEMLOC Memory Location Select: Read only. Set to 0 by the RTL8101L. This indicates that the base register is
32-bit wide and can be placed anywhere in the 32-bit memory space.
0
MEMIN
Memory Space Indicator: Read only. Set to 0 by the RTL8101L to indicate that it is capable of being
mapped into memory space.
SVID: Subsystem Vendor ID. This field will be set to a value corresponding to PCI Subsystem Vendor ID in the external
EEPROM. If there is no EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI
Subsystem Vendor ID.
SMID: Subsystem ID. This field will be set to value corresponding to PCI Subsystem ID in the external EEPROM. If there is no
EEPROM, this field will default to a value of 8139h.
BMAR: This register specifies the base memory address for memory accesses to the RTL8139C(L) operational registers. This
register must be initialized prior to accessing any RTL8139C(L)'s register with memory access.
Bit
Symbol
Description
31-18
BMAR31-18
Boot ROM Base Address
17-11
ROMSIZE
These bits indicate how many Boot ROM spaces to be supported.
The Relationship between Config 0 <BS2:0> and BMAR17-11 is the following:
BS2 BS1 BS0 Description
0 0 0 No Boot ROM, BROMEN=0 (R)
0 0 1 8K Boot ROM, BROMEN (R/W), BMAR12-11 = 0 (R), BMAR17-13 (R/W)
0 1 0 16K Boot ROM, BROMEN (R/W), BMAR13-11 = 0 (R), BMAR17-14 (R/W)
0 1 1 32K Boot ROM, BROMEN (R/W), BMAR14-11 = 0 (R), BMAR17-15 (R/W)
1 0 0 64K Boot ROM, BROMEN (R/W), BMAR15-11 = 0 (R), BMAR17-16 (R/W)
1 0 1 128K Boot ROM, BROMEN(R/W), BMAR16-11=0 (R), BMAR17 (R/W)
1 1 0 unused
1 1 1 unused
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