RTL8101L
2003-05-28
Rev.1.3
47
4
MWIEN
Memory Write and Invalidate cycle Enable: Read as 0, write operation has no effect.
3
SCYCEN
Special Cycle Enable: Read as 0, write operation has no effect. The RTL8101L ignores all special
cycle operation.
2
BMEN
Bus Master Enable: When set to 1, the RTL8101L is capable of acting as a bus master. When set to 0,
it is prohibited from acting as a PCI bus master.
For the normal operation, this bit must be set by the system BIOS.
1
MEMEN
Memory Space Access: When set to 1, the RTL8101L responds to memory space accesses. When set
to 0, the RTL8101L ignores memory space accesses.
0
IOEN
I/O Space Access: When set to 1, the RTL8101L responds to IO space access. When set to 0, the
RTL8101L ignores I/O space accesses.
Status: The status register is a 16-bit register used to record status information for PCI bus related events. Reads to this register
behave normally. Writes are slightly different in that bits can be reset, but not set.
Bit
Symbol
Description
15
DPERR
Detected Parity Error: When set indicates that the RTL8101L detected a parity error, even if parity
error handling is disabled in command register PERRSP bit.
14
SSERR
Signaled System Error: When set indicates that the RTL8101L asserted the system error pin, SERRB.
Writing a 1 clears this bit to 0.
13
RMABT
Received Master Abort: When set indicates that the RTL8101L terminated a master transaction with
master abort. Writing a 1 clears this bit to 0.
12
RTABT
Received Target Abort: When set indicates that the RTL8101L master transaction was terminated due to
a target abort. Writing a 1 clears this bit to 0.
11
STABT
Signaled Target Abort: Set to 1 whenever the RTL8101L terminates a transaction with target abort.
Writing a 1 clears this bit to 0.
10-9
DST1-0
Device Select Timing: These bits encode the timing of DEVSELB. They are set to 01b (medium),
indicating the RTL8101L will assert DEVSELB two clocks after FRAMEB is asserted.
8
DPD
Data Parity error Detected:
This bit sets when the following conditions are met:
※
The RTL8101L asserts parity error(PERRB pin) or it senses the assertion of PERRB pin by another device.
※
The RTL8101L operates as a bus master for the operation that caused the error.
※
The Command register PERRSP bit is set.
Writing a 1 clears this bit to 0.
7
FBBC
Fast Back-To-Back Capable: Config3<FbtBEn>=0, Read as 0, write operation has no effect.
Config3<FbtBEn>=1, Read as 1.
6
UDF
User Definable Features Supported: Read as 0, write operation has no effect. The RTL8101L does not
support UDF.
5
66MHz
66 MHz Capable: Read as 0, write operation has no effect. The RTL8101L has no 66MHz capability.
4
NewCap
New Capability: Config3<PMEn>=0, Read as 0, write operation has no effect. Config3<PMEn>=1,
Read as 1.
0-3
-
Reserved
RID: Revision ID Register
The Revision ID register is an 8-bit register that specifies the RTL8101L controller revision number.
PIFR: Programming Interface Register
The programming interface register is an 8-bit register that identifies the programming interface of the RTL8101L controller.
Because the PCI version 2.1 specification does not define any specific value for network devices, PIFR = 00h.
SCR: Sub-Class Register
The Sub-class register is an 8-bit register that identifies the function of the RTL8101L. SCR = 00h indicates that the
RTL8101L is an Ethernet controller.
BCR: Base-Class Register
The Base-class register is an 8-bit register that broadly classifies the function of the RTL8101L. BCR = 02h indicates that
the RTL8101L is a network controller.
CLS: Cache Line Size
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