RTL8101L
2003-05-28
Rev.1.3
46
3Eh
MNGNT
R
0
0
1
0
0
0
0
0
3Fh
MXLAT
R
0
0
1
0
0
0
0
0
40h–4
Fh
RESERVED
50h
PMID
R
0
0
0
0
0
0
0
1
51h
NextPtr
R
0
0
0
0
0
0
0
0
52h
PMC
R
Aux_I_b1
Aux_I_b0
DSI
Reserved PMECLK
Version
53h
R
PME_D3cold PME_D3hot PME_D2 PME_D1 PME_D0
D2
D1
Aux_I_b2
54h
PMCSR
R
0
0
0
0
0
0
Power State
W
-
-
-
-
-
-
Power State
55h
R
PME_Status
-
-
-
-
-
-
PME_En
W
PME_Status
-
-
-
-
-
-
PME_En
56h–5
Fh
RESERVED
60h
VPDID
R
0
0
0
0
0
0
1
1
61h
NextPtr
R
0
0
0
0
0
0
0
0
62h
Flag VPD
Address
R/W VPDADDR
7
VPDADDR
6
VPDADD
R5
VPDADD
R4
VPDADD
R3
VPDADD
R2
VPDADD
R1
VPDADD
R0
63h
R/W
Flag
VPDADDR
14
VPDADD
R13
VPDADD
R12
VPDADD
R11
VPDADD
R10
VPDADD
R9
VPDADD
R8
64h
R/W
Data7
Data6
Data5
Data4
Data3
Data2
Data1
Data0
65h
R/W
Data15
Data14
Data13
Data12
Data11
Data10
Data9
Data8
66h
R/W
Data23
Data22
Data21
Data20
Data19
Data18
Data17
Data16
67h
VPD Data
R/W
Data31
Data30
Data29
Data28
Data27
Data26
Data25
Data24
68h-F
Fh
RESERVED
8.2 PCI Configuration Space functions
The PCI configuration space is intended for configuration, initialization, and catastrophic error handling functions. The functions
of the RTL8101L's configuration space are described below.
VID: Vendor ID. This field will default to a value of 10ECh which is Realtek Semiconductor's PCI Vendor ID.
DID: Device ID. This field will default to a value of 8139h.
Command: The command register is a 16-bit register used to provide coarse control over a device's ability to generate and
respond to PCI cycles.
Bit
Symbol
Description
15-10
-
Reserved
9
FBTBEN
Fast Back-To-Back Enable: Config3<FBtBEn>=0:Read as 0. Write operation has no effect. The
RTL8101L will not generate Fast Back-to-back cycles. When Config3<FbtBEn>=1, This read/write
bit controls whether or not a master can do fast back-to-back transactions to different devices.
Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means the
master is allowed to generate fast back-to-back transaction to different agents. A value of 0 means fast
back-to-back transactions are only allowed to the same agent. This bit’s state after RST# is 0.
8
SERREN
System Error Enable: When set to 1, the RTL8101L asserts the SERRB pin when it detects a parity
error on the address phase (AD<31:0> and CBEB<3:0> ).
7
ADSTEP
Address/Data Stepping: Read as 0, write operation has no effect. The RTL8101L never make
address/data stepping.
6
PERRSP
Parity Error Response: When set to 1, the RTL8101L will assert the PERRB pin on the detection of
a data parity error when acting as the target, and will sample the PERRB pin as the master. When set to
0, any detected parity error is ignored and the RTL8101L continues normal operation.
Parity checking is disabled after hardware reset (RSTB).
5
VGASNOOP VGA palette SNOOP: Read as 0, write operation has no effect.
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