RTL8101L
2003-05-28
Rev.1.3
43
Do not change this field without Realtek approval.
1Fh
CONFIG_5
Bit7-6: Reserved.
Bit5-4: Multi-function Select:
00b: Ethernet Controller Only
01b: MC’97 Controller Only
10b: Ethernet+MC’97 Controllers
11b:After ver F Ethernet+Auto detect MC’97 Controllers
If 8101L detected MC’97 clock the 8101L set to Multi-function. Otherwise it
set to Ethernet only. Only detect the MC’97 while power on reset.
From A to E version: Ethernet+MC’97 Controllers
Bit3: Reserved.
Bit2: Link Down Power Saving mode:
Set to 1: Disable.
Set to 0: Enable. When cable is disconnected(Link Down), the analog part will power
down itself (PHY Tx part & part of twister) automatically except PHY Rx part and
part of twister to monitor SD signal in case that cable is re-connected and Link should
be established again.
Bit1: LANWake signal Enable/Disable
Set to 1: Enable LANWake signal.
Set to 0: Disable LANWake signal.
Bit0: PME_Status bit property
Set to 1: The PME_Status bit can be reset by PCI reset or by software if
D3cold_support_PME is 0. If D3cold_support_PME=1, the PME_Status bit is a
sticky bit.
Set to 0: The PME_Status bit is always a sticky bit and can only be reset by software.
20h-21h
MC97_VID
Vendor ID of MC’97 Controller.
22h-23h
MC97_DID
Device ID of MC’97 Controller.
24h-25h
MC97_SVID
Sub-Vendor ID of MC’97 Controller.
26h-27h
MC97_SDID
Sub-Device ID of MC’97 Controller.
28h-2Bh
PHY1_PARM_T
Reserved. Do not change this field without Realtek approval.
PHY Parameter 1-T for RTL8101L. Operational registers of the RTL8101L are from 78h
to 7Bh.
2Ch
PHY2_PARM_T
Reserved. Do not change this field without Realtek approval.
2Dh-31h
-
Reserved.
32h-33h
CheckSum
Reserved. Do not change this field without Realtek approval.
Checksum of the EEPROM content.
34h-3Eh
-
Reserved. Do not change this field without Realtek approval.
3Fh
PXE_Para
Reserved. Do not change this field without Realtek approval.
PXE ROM code parameter.
40h-7Fh
VPD_Data
VPD data field. Offset 40h is the start address of the VPD data.
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