RTL8101L datasheet(42/68 Pages) ETC1

Part #	RTL8101L

Description	REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC97 CONTROLLER WITH POWER MANAGEMENT

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RTL8101L

2003-05-28

Rev.1.3

42

7. EEPROM (93C46) Contents

The 93C46 is a 1K-bit EEPROM. Although it is actually addressed by words, its contents are listed below by bytes for

convenience. After the valid duration of the RSTB pin or auto-load command in the 9346CR, the RTL8101L performs a series of

EEPROM read operations from the 93C46 addresses 00H to 31H.

It is suggested to obtain Realtek approval before changing the default settings of the EEPROM.

Bytes

Contents

Description

00h

29h

01h

81h

These 2 bytes contain the ID code word for the RTL8101L. The RTL8101L will load the

contents of EEPROM into the corresponding location if the ID word (8129h) is right,

otherwise, the RTL8101L will not proceed with the EEPROM autoload process.

02h-05h

-

Reserved. The RTL8101L no longer supports autoload of Vender ID and Device ID. The

default values of VID and DID are hex 10EC and 8139, respectively.

06h-07h

SVID

PCI Subsystem Vendor ID, PCI configuration space offset 2Ch-2Dh.

08h-09h

SMID

PCI Subsystem ID, PCI configuration space offset 2Eh-2Fh.

0Ah

MNGNT

PCI Minimum Grant Timer, PCI configuration space offset 3Eh.

0Bh

MXLAT

PCI Maximum Latency Timer, PCI configuration space offset 3Fh.

0Ch

MSRBMCR

Bits 7-6 map to bits 7-6 of the Media Status register (MSR); Bits 5, 4, 0 map to bits 13,

12, 8 of the Basic Mode Control register (BMCR); Bits 3-2 are reserved. If the network

speed is set to Auto-Detect mode (i.e. Nway mode), then Bit 1=0 means the local

RTL8101L supports flow control (IEEE 802.3x). In this case, Bit 10=1 in the

Auto-negotiation Advertisement Register (offset 66h-67h), and Bit 1=1 means the local

RTL8101L does not support flow control. In this case, Bit 10=0 in Auto-negotiation

Advertisement. This is because there are Nway switch hubs which keep sending flow

control pause packets for no reason, if the link partner supports Nway flow control.

0Dh

CONFIG3

RTL8101L Configuration register 3, operational register offset 59H.

0Eh-13h

Ethernet ID

Ethernet ID, After auto-load command or hardware reset, RTL8101L loads Ethernet ID

to IDR0-IDR5 of RTL8101L's I/O registers.

14h

CONFIG0

RTL8101L Configuration register 0, operational registers offset 51h.

15h

CONFIG1

RTL8101L Configuration register 1, operational registers offset 52h.

16h-17h

PMC