RTL8101L datasheet(41/68 Pages) ETC1

Part #	RTL8101L

Description	REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC97 CONTROLLER WITH POWER MANAGEMENT

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RTL8101L

2003-05-28

Rev.1.3

41

I:

When it is set to a 1 by S/W, the controller should issue an interrupt upon completion of this buffer.

BU:

If it is set to a 0, the controller should continuously send the last valid data when FIFO is under-run. (Keep the last data, and

validates the tag bit for Slot-5 on AC_DOUT)

If it is set 1, the controller continuously send the last invalid data when FIFO is empty or under-run. (Keep the last data, but

invalidates the tag bit for Slot-5 on AC_DOUT)

(The BU bit is only effective for LINE1-Out master)

Buffer Length [14:0]:

The size of data buffer is in number of 16-bit sample. So the maximum number of samples is 32767. A value of 0 means there is no

sample transferred into this buffer. To achieve an efficient PCI transaction, the buffer length must be an even number.

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