RTL8101L
2003-05-28
Rev.1.3
39
6.22 PCI GPIO Status Register
(Offset 002Eh-002Fh, R/W)
Bit
R/W
Symbol
Description
15-10
-
-
Reserved
9
R/W
PCIGPIO1_PMES
PCIGPIO1 PME# Event Status:
❶
1: PCIGPIO1 PME# event has been occurred in D3 state.
0: No PCIGPIO1 PME# event has been occurred in D3 state.
Write a 1 to clear this status bit.
8
R/W
PCIGPIO0_PMES
PCIGPIO0 PME# Event Status:
❶
1: PCIGPIO0 PME# event has been occurred in D3 state.
0: No PCIGPIO0 PME# event has been occurred in D3 state.
Write a 1 to clear this status bit.
7-2
-
-
Reserved
1
R/W
PCIGPIO1_IOS
PCIGPIO1 Input/Output Status:
❷
1: PCIGPIO1 is driven high by external device (input).
/ Drive PCIGPIO1 high (output).
0: PCIGPIO1 is driven low by external device (input).
/ Drive PCIGPIO1 low (output).
0
R/W
PCIGPIO0_IOS
PCIGPIO0 Input/Output Status:
❷
1: PCIGPIO0 is driven high by external device (input).
/ Drive PCIGPIO0 high (output).
0: PCIGPIO0 is driven low by external device (input).
/ Drive PCIGPIO0 low (output).
❶ When this pin is used as input.
❷ PCIGPIOSR[9:8] and PCIGPIOSR[1:0] are sticky bits like as PME_Status (PMCSR.15) and PME_EN (PMCSR.8) be power
by Vaux.
6.23 EEPROM (93C46) Command Register
(Offset 0030h, R/W)
Bit
R/W
Symbol
Description
7-6
R/W
EEM1-0
Operating Mode: These 2 bits select the RTL8101L operating mode.
EEM1
EEM0
Operating Mode
0
0
Normal (RTL8101L network/host communication mode)
0
1
Auto-load: Entering this mode will make the RTL8101L
load the contents of 93C46 like when the RSTB signal is
asserted. This auto-load operation will take about 2 ms.
After it is completed, the RTL8101L goes back to the
normal mode automatically (EEM1 = EEM0 = 0) and all
the other registers are reset to default values.
1
0
93C46 programming: In this mode, both network and
host bus master operations are disabled. The 93C46 can
be directly accessed via bit3-0 which now reflect the
states of EECS, EESK, EEDI, & EEDO pins respectively.
1
1
Config register write enable: Before writing to CONFIG0,
1, 3, 4 registers, and bit13, 12, 8 of BMCR(offset
62h-63h), the RTL8101L must be placed in this mode.
This will prevent RTL8101L's configurations from
accidental change.
4-5
-
-
Reserved
3
R/W
EECS
2
R/W
EESK
These bits reflect the state of EECS, EESK, EEDI & EEDO pins in
auto-load or 93C46 programming mode.
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