RTL8101L
2003-05-28
Rev.1.3
37
4
R/W
ACLINK_WES
AC-LINK Wake-up Event Status:
1: AC-LINK wake-up event occurred.
0: No wake-up event.
This bit is set if ACLINK wake-up event is detected. This controller will
generate an interrupt when (ACLINK_WES=1) & (ACLINK_WIE=1).
Writing a ‘1’ to clear this bit, and its interrupt.
This bit will not be set when ACLINK Shut-Off (ACCR.3) is 0. Once it
is set by an ACLINK wake-up event, it can only be cleared after
ACLINK Shut-Off is cleared.
3
R/W
FIFO_un
LINE1-Out FIFO Under-run:
1: FIFO error indicates a FIFO under-run. And it will cause an interrupt
if the enable bit in LINE1-Out’s Control Register is set. This bit and its
interrupt should be cleared by written a ‘1’.
2
R/W
LO_Curr_End
Completion of current Line1-Out’s descriptor:
1: The current LINE1-Out’s descriptor has got the last sample from
system memory. And it will cause an interrupt if the enable bit in Control
Register is set. This bit and its interrupt should be cleared by writting a
‘1’.
1
R/W
LO_Last_End
Completion of the last LINE1-Out’s descriptor:
1: The last descriptor has got the last sample from system memory. And
it will cause an interrupt if the enable bit in Control Register is set. This
bit and its interrupt should be cleared by writing a ‘1’.
0
R/W
GPIS
MC97 GPIO Interrupt Status:
1: MC97 GPIO interrupt. The GPIO_INT (ACSIR.8) has ever been set.
0: No MC97 GPIO interrupt.
This bit is set if GPIO_INT (ACSIR.8) has ever been set. This controller
will generate an interrupt when (GPIS=1) & (GPIE=1).
Writing a ‘1’ will clear this bit and its interrupt.
❶ Bit 4 is sticky bit preserved by consuming power from Vaux.
❷ When PCIGPIOx pin is used as input.
6.21 PCI GPIO Setup Register
(Offset 002Ch-002Dh, R/W)
Bit
R/W
Symbol
Description
15-10
-
-
Reserved
9
R/W
PCIGPIO1_PEE
PCIGPIO1 PME# Event Enable (when PCIGPIO1 is used as input):
❶❷
1: Enable
0: Disable
A low to high transaction on PCIGPIO1 will trigger the PCI PME# in D3
state.
8
R/W
PCIGPIO0_PEE
PCIGPIO0 PME# Event Enable (when PCIGPIO0 is used as input):
❶❷
1: Enable
0: Disable
A low to high transaction on PCIGPIO0 will trigger the PCI PME# in D3
state.
7-6
-
-
Reserved
5
R/W
PCIGPIO1_IE
PCIGPIO1 interrupt Enable (when PCIGPIO1 is used as input):
1: Enable
0: Disable
A low to high transaction PCIGPIO1 will trigger the PCI interrupt.
4
R/W
PCIGPIO0_IE
PCIGPIO0 interrupt Enable (when PCIGPIO0 is used as input):
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