RTL8101L
2003-05-28
Rev.1.3
36
(Offset 0026h - 0027h, R/W)
Bit
R/W
Symbol
Description
15-0
R/W
GPIOOD
MC97’s GPIO output data.
❶ Bit [15:0] control the GPIO [15:0] output of MC97. Bit 15~0 are sent on SDATA-OUT slot-12 bit 19 to bit 4.
❷ Software should check ACSIR.9 (GPIO_Busy) before writing data. If GPIO_Busy is set by hardware and bit[15:0] are changed,
any pending data will be overwritten.
6.19 Real Time GPIO Input Data From MC’97
(Offset 0028h - 0029h, RO)
Bit
R/W
Symbol
Description
15-0
R
GPIOID
MC97’s GPIO input data.
❶ These bits reflect the real time GPIO input status on SDATA-IN from MC97. Bit 15~0 are latched from SDATA-IN input slot
12 bit 19~4 when data is valid.
❷ These bits are real-time updated according to SDATA-IN slot-12 in every frame.
6.20 Interrupt Status Register
(Offset 002Ah-002Bh, R/W)
Bit
R/W
Symbol
Description
15
R/W
SERR_IE
SERR# Interrupt Enable:
1: Enable interrupt when RTL8101L signals SERR# on PCI bus
0: Disable
14
R/W
SERR_IS
SERR# Interrupt Status:
1: SERR# interrupt, RTL8101L signals SERR# on PCI bus.
0: No SERR# interrupt.
This controller will generate an SERR# interrupt when (SERR_IE=1) &
(SERR# Status=1, Status[14] in configuration space).
Write a ‘1’ to clear this bit and its interrupt.
13-10
-
-
Reserved
9
R/W
PCIGPIO1_IS·
PCIGPIO1 Interrupt Status:
1: PCIGPIO1 interrupt.
0: No PCIGPIO1 interrupt.
Write 1 to clear this status bit and its interrupt.
8
R/W
PCIGPIO0_IS
PCIGPIO0 Interrupt Status:
1: PCIGPIO0 interrupt.
0: No PCIGPIO0 interrupt.
Write 1 to clear this status bit and its interrupt.
7
R/W
FIFO_ov
LINE-In’s FIFO Over-run:
1: FIFO error indicates a FIFO over-run. And it will cause an interrupt if
theenable bit in Control Register is set. This bit and its interrupt should
be cleared by written a ‘1’. The data received after overrun occurs will
not come into FIFO.
6
R/W
LI_Curr_End
Completion of current LINE-In’s descriptor:
1: The current descriptor has sent the last sample to system memory. And
it will cause an interrupt if the enable bit in Control Register is set. This
bit and its interrupt should be cleared by written a ‘1’.
5
R/W
LI_Last_End
Completion of the last LINE-In’s descriptor:
1: The last descriptor has sent the last sample to system memory. And it
will cause an interrupt if the enable bit in Control Register is set. This bit
and its interrupt should be cleared by written a ‘1’.
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