RTL8101L
2003-05-28
Rev.1.3
34
6.15 MC’97-Link Control Register
(Offset 0020h-0021h, R/W)
Bit
R/W
Symbol
Description
15-8
-
-
Reserved
7
R/W
MCSDLB
1: MC97_SDATAIN source comes from MC97_SDATAOUT.
0: Normal (MC97_SDATAIN source comes from MC97)
6
-
-
Reserved
5
R/W
ACLINK_WPE
AC-LINK Wake-up PME# Enable:
❶❷
1: Enable a PME# when MC’97 issues a wake-up event on MC-LINK.
0: Disable
If it is disabled, AC-LINK wake-up event doesn’t set PME_Status
(PCR4C.15), but AC-LINK wake-up event (ACLINK_WES) is still
indicated in INTSR.4.
4
R/W
ACLINK_WIE
AC-LINK Wake-up Interrupt Enable:
❶
1: Enable an interrupt when MC’97 issues a wake-up event on AC-LINK.
0: Disable
If it is disabled, AC-LINK wake-up event doesn’t trigger interrupt, but
AC-LINK wake-up event (ACLINK_WES) is still indicated in INTSR.4
3
R/W
ACLINK_OFF
AC-LINK Shut Off:
❷
1: Drive all AC-LINK outputs low if AC97_BITCLK is stopped, also
disable Line-In buffer. It’s software’s responsibility to set this bit after
power-down MC’97 command to enable AC-LINK wake-up event
function. It means that wake-up functions defined in bit[5:4] and
ACLINK_WES (INTSR.4) will be effective when this bit is set.
0: Normal operation
2
R/W
ACLINK_WRST
MC’97 Warm Reset:
1: Writing a ‘1’ to drive AC97_SYNC high at least 1.2us
Writing a ‘1’ to this bit only effective while AC97_BITCLK is stopped.
If software wants to issue a warm reset while AC97_BITCLK is running,
the write is ignored and this bit is unchanged.
0: No effect (normal)
This bit is auto cleared by hardware after warm reset had been issued.
1
R/W
ACLINK_CRST
MC’97 Cold Reset:
1: Writing a ‘1’ to drive AC97_RESET# low at least 1.2 us.
0: No effect (normal, AC97_RESET# kept as high.)
This bit is auto set by hardware after cold reset had been issued.
0
R/W
GPIE
GPI Interrupt Enable:
1: The change on GPI Interrupt Status (AC-LINK status bit-0 of slot-12)
will cause an interrupt on PCI interface.
0: Interrupt is not generated even GPI Interrupt Status is set.
❶ AC-LINK wake-up event: AC97_SDATAIN is resumed a high while AC-LINK signals are shut off.
❷ Bit 5 and bit 3 are sticky bits preserved by consuming power from Vaux.
6.16 MC’97-Link Status and Index Register
(Offset 0022h-0023h, R/W)
Bit
R/W
Symbol
Description
15
R
ACLINK_BZ
AC-LINK busy:
1: AC-LINK is busy on a MC’97 register read/write transaction.
0: No access is in progress
It is set when controller is doing an AC-LINK read/write transaction, it is
auto cleared by hardware after the transaction has been finished or
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