RTL8101L
2003-05-28
Rev.1.3
33
(Offset 0014h-0015h, R/W)
Bit
R/W
Symbol
Description
15-12
-
-
Reserved
11-8
R/W
LI_DMA_TH
LINE-In DMA Threshold Control:
0,1: When FIFO is empty, DMA will be triggered.
2,3: When sample number in FIFO >= 2, DMA will be triggered.
…
E,F: When sample number in FIFO >=14, DMA will be triggered.
Once LINE-In DMA is triggered, DMA will continuously read from
System memory until samples number in FIFO is equal to threshold.
7
R/W
LI_RS_DMA
Set to clear all registers (offset at 0010h ~ 0017h) related to DMA, and
output FIFO should be flushed. This bit is auto cleared and should be set
only when DMA is halted.
6-5
-
-
Reserved
4
R/W
FIFOOVIE
FIFO Over-Run Interrupt Enable:
1: Enable interrupt caused by FIFO over-run.
0: Disable interrupt caused by FIFO over-run even the ‘FIFO_ov’ is set.
3
R/W
LI_CDIE
Current Descriptor Interrupt Enable:
1: Enable interrupt caused by current descriptor has finished its transaction.
0: Disable interrupt caused by current descriptor even the ‘Curr_End’ is set.
2
R/W
LI_LDIE
Last Descriptor Interrupt Enable:
1: Enable interrupt caused by the last descriptor has finished its transaction.
0: Disable interrupt caused by the last descriptor even the ‘Last_End’ is set.
1
R/W
LI_PDMA
Pause LINE-In DMA:
1: The LINE1-In DMA is paused. FIFO send to PCI bus is frozen, data in
FIFO received from AC-LINK is flushed, whether controller should
continuously send the latest data before FIFO froze depends on the BU
setting for descriptor.
0: resume DMA
0
R/W
LI_Start
LINE-In DMA Start/Stop:
1: Start bus master transaction, and the first descriptor assigned in
“Starting Descriptor Index”.
0: Stop bus master transaction
6.13 Residual Samples Count in Current LINE-In Descriptor Register
(Offset 0016h - 0017h, R/W)
Bit
R/W
Symbol
Description
15-0
R
LI_RSS
The residual samples number should be read in system memory for
current descriptor. (sample: a 16-bit word)
6.14 Line-In Descriptor Base Address Register
(Offset 001Ch – 001Fh, R/W)
Bit
R/W
Symbol
Description
31-2
R/W
LINE-In Descriptor Base Address [31:2].
1-0
R
LI_DBA
LINE-In Descriptor Base Address [1:0]. Hardwired to 0.
❶The LINE-In Descriptor Base Address (LI_DBA) points to the starting address of continuous 64 double WORD descriptor’s
DMA context stored in main memory.
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