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RTL8101L Datasheet(PDF) 31 Page - List of Unclassifed Manufacturers

Part # RTL8101L
Description  REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC97 CONTROLLER WITH POWER MANAGEMENT
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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RTL8101L
2003-05-28
Rev.1.3
31
4-0
R
LO_LDILO
Assign the last descriptor to be run. After the last transaction has been
completed for this last descriptor, LINE-Out bus master should stop.
6.4 LINE-Out DMA Status Register
(Offset 0003h, RO)
Bit
R/W
Symbol
Description
7-2
-
-
Reserved
1
R
LO_Curr_Last
Current descriptor is the last descriptor. This bit will be auto cleared
0
R
LO_LH
The LINE-Out bus master is not active or the last descriptor has finished
transaction. This bit will be auto cleared by H/W when bus master is active.
6.5 LINE-Out DMA Control Register
(Offset 0004h-0005h, R/W)
Bit
R/W
Symbol
Description
15-12
-
-
Reserved
11-8
R/W
LO_DMA_TH
LINE-OUT DMA Threshold Control:
0,1: When FIFO is empty, DMA will be triggered.
2,3: When sample number in FIFO < 2, DMA will be triggered.
E,F: When sample number in FIFO < 14, DMA will be triggered.
Once LINE1-Out DMA is triggered, DMA will continuously read from
System memory until samples number in FIFO is equal to threshold.
7
R/W
LO_RS_DMA
Set to clear all registers (offset at 0000h ~ 0007h) related to DMA, and
output FIFO should be flushed. This bit is auto cleared and should be set
only when DMA is halted.
6-5
-
-
Reserved
4
R/W
FIFOUNIE
FIFO Under-Run Interrupt Enable:
1: Enable interrupt caused by FIFO under-run.
0: Disable interrupt caused by FIFO under-run even the ‘FIFO_un’ is set.
3
R/W
LO_CDIE
Current Descriptor Interrupt Enable:
1: Enable interrupt caused by current descriptor has finished its transaction.
0: Disable interrupt caused by current descriptor even the ‘Curr_End’ is set.
2
R/W
LO_LDIE
Last Descriptor Interrupt Enable:
1: Enable interrupt caused by the last descriptor has finished its transaction.
0: Disable interrupt caused by the last descriptor even the ‘Last_End’ is set.
1
R/W
LO_PDMA
Pause LINE-Out DMA:
1: The LINE1-Out DMA is paused. FIFO request to PCI bus is frozen,
residual data in FIFO send to AC-LINK is also froze, whether controller
should continuously send the latest data before FIFO froze depends on
the BU setting for descriptor.
0: resume DMA
0
R/W
LO_Start
LINE-Out DMA Start/Stop:
1: Start bus master transaction, and the first descriptor assigned in
“Starting Descriptor Index”.
0: Stop bus master transaction
6.6 Residual Samples Count in Current LINE-Out Descriptor Register


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