RTL8101L
2003-05-28
Rev.1.3
23
If the Node ID is 11h 22h 33h 44h 55h 66h, then the magic frame’s
format is similar to the following:
Destination address + source address + MISC + FF FF FF FF FF FF +
MISC + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11
22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44
55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11
22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44
55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + MISC + CRC
4
R/W
LinkUp
Link Up: This bit is valid when the PWEn bit of CONFIG1 register is
set. The RTL8101L, in adequate power state, will assert the PMEB
signal to wakeup the operating system when the cable connection is
re-established.
3-1
-
-
Reserved
2
R
CLKRUN_En
CLKRUN Enable:
1: Enable CLKRUN
0: Disable CLKRUN
1
-
-
Reserved
0
R
FBtBEn
Fast Back to Back Enable: Set to 1 to enable Fast Back to Back.
5.14 CONFIG 4: Configuration Register4
(Offset 005Ah, R/W)
Bit
R/W
Symbol
Description
7
R/W
RxFIFOAutoClr
Set to 1, the RTL8101L will clear the Rx FIFO overflow automatically.
6
R/W
AnaOff
Analog Power Off: This bit can not be auto-loaded from EEPROM
(93C46).
1: Turn off the analog power of the RTL8101L internally.
0: Normal working state. This is also power-on default value.
5
R/W
LongWF
Long Wake-up Frame: The initial value comes from EEPROM
autoload.
Set to 1: The RTL8101L supports up to 5 wake-up frames, each with
16-bit CRC algorithm for MS Wakeup Frame, the low byte of 16-bit
CRC should be placed at the correspondent CRC register, and the high
byte of 16-bit CRC should be placed at the correspondent LSBCRC
register. The wake-up frame 0 and 1 are the same as above, except that
the masked bytes start from offset 0 to 63. The wake-up frame 2 and 3
are merged into one long wake-up frame respectively with masked bytes
selected from offset 0 to 127. The wake-up frame 4 and 5, 6 and 7 are
merged respectively into another 2 long wake-up frames. Please refer to
7.4 PCI Power Management functions for detailed description.
Set to 0: The RTL8101L supports up to 8 wake-up frames, each with
masked bytes selected from offset 12 to 75.
4
R/W
LWPME
LANWAKE vs PMEB:
Set to 1: The LWAKE can only be asserted when the PMEB is asserted
and the ISOLATEB is low.
Set to 0: The LWAKE and PMEB are asserted at the same time.
3
-
-
Reserved
2
R/W
LWPTN
LWAKE pattern: Please refer to LWACT bit in CONFIG1 register.
1
-
-
Reserved
0
R/W
PBWakeup
Pre-Boot Wakeup: The initial value comes from EEPROM autoload.
1: Pre-Boot Wakeup disabled. (suitable for CardBus and MiniPCI
applications)
0: Pre-Boot Wakeup enabled.
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