RTL8101L
2003-05-28
Rev.1.3
19
15-13
R/W
RXFTH2, 1, 0
Rx FIFO Threshold: Specifies Rx FIFO Threshold level. When the
number of the received data bytes from a packet, which is being received
into the RTL8101L's Rx FIFO, has reached to this level (or the FIFO has
contained a complete packet), the receive PCI bus master function will
begin to transfer the data from the FIFO to the host memory. This field sets
the threshold level according to the following table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = no rx threshold. The RTL8101L begins the transfer of data after
having received a whole packet in the FIFO.
12-11
R/W
RBLEN1, 0
Rx Buffer Length: This field indicates the size of the Rx ring buffer.
00 = 8k + 16 byte
01 = 16k + 16 byte
10 = 32K + 16 byte
11 = 64K + 16 byte
10-8
R/W
MXDMA2, 1, 0
Max DMA Burst Size per Rx DMA Burst: This field sets the maximum
size of the receive DMA data bursts according to the following table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = unlimited
7
R/W
WRAP
When set to 0: The RTL8101L will transfer the rest of the packet data
into the beginning of the Rx buffer if this packet has not been completely
moved into the Rx buffer and the transfer has arrived at the end of the Rx
buffer.
When set to 1: The RTL8101L will keep moving the rest of the packet
data into the memory immediately after the end of the Rx buffer, if this
packet has not been completely moved into the Rx buffer and the transfer
has arrived at the end of the Rx buffer. The software driver must reserve
at least 1.5K bytes buffer to accept the remainder of the packet. We
assume that the remainder of the packet is X bytes. The next packet will
be moved into the memory from the X byte offset at the top of the Rx
buffer.
This bit is invalid when Rx buffer is selected to 64K bytes.
6
-
-
Reserved
5
R/W
AER
Accept Error Packet: When set to 1, all packets with CRC error,
alignment error, and/or collided fragments will be accepted. When set to
0, all packets with CRC error, alignment error, and/or collided fragments
will be rejected.
4
R/W
AR
Accept Runt: This bit allows the receiver to accept packets that are
smaller than 64 bytes. The packet must be at least 8 bytes long to be
accepted as a runt. Set to 1 to accept runt packets.
3
R/W
AB
Accept Broadcast packets: Set to 1 to accept, 0 to reject.
2
R/W
AM
Accept Multicast packets: Set to 1 to accept, 0 to reject.
1
R/W
APM
Accept Physical Match packets: Set to 1 to accept, 0 to reject.
0
R/W
AAP
Accept All Packets: Set to 1 to accept all packets with a physical
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