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RTL8101L Datasheet(PDF) 16 Page - List of Unclassifed Manufacturers

Part # RTL8101L
Description  REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC97 CONTROLLER WITH POWER MANAGEMENT
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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RTL8101L Datasheet(HTML) 16 Page - List of Unclassifed Manufacturers

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RTL8101L
2003-05-28
Rev.1.3
16
due to excessive collisions, according to the TXRR's setting.
2
R/W
TOK
Transmit (Tx) OK: Indicates that a packet transmission is completed
successfully.
1
R/W
RER
Receive (Rx) Error: Indicates that a packet has either CRC error or
frame alignment error (FAE). The collided frame will not be recognized
as CRC error if the length of this frame is shorter than 16 byte.
0
R/W
ROK
Receive (Rx) OK: In normal mode, indicates the successful completion
of a packet reception. In early mode, indicates that the Rx byte count of
the arriving packet exceeds the early Rx threshold.
5.7 Transmit Configuration Register
(Offset 0040h-0043h, R/W)
This register defines the Transmit Configuration for the RTL8101L. It controls such functions as Loopback, Heartbeat, Auto
Transmit Padding, programmable Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size.
Bit
R/W
Symbol
Description
31
-
-
Reserved
Hardware Version ID A:
Bit30 Bit29 Bit28 Bit27 Bit26 Bit23 Bit22
RTL8139
1
1
0
0
0
0
0
RTL8139A
1
1
1
0
0
0
0
RTL8139A-G
1
1
1
0
1
0
0
RTL8139B
1
1
1
1
0
0
0
RTL8130
1
1
1
1
0
0
0
RTL8139C
1
1
1
0
1
0
0
RTL8100
1
1
1
1
0
1
0
RTL8100(B)/
8102
1
1
1
0
1
0
1
RTL8139C+
1
1
1
0
1
1
0
RTL8101L
1
1
1
0
1
1
1
Reserved
Other combination
30-26
R
HWVERID_A
25-24
R/W
IFG1, 0
Interframe Gap Time: This field allows the user to adjust the
interframe gap time below the standard: 9.6 us for 10Mbps, 960 ns for
100Mbps. The time can be programmed from 9.6 us to 8.4 us (10Mbps)
and 960ns to 840ns (100Mbps). Note that any value other than (1, 1) will
violate the IEEE 802.3 standard.
The formula for the inter frame gap is:
10 Mbps
8.4us + 0.4(IFG(1:0)) us
100 Mbps
840ns + 40(IFG(1:0)) ns
23-22
R
HWVERID_B
Hardware Version ID B
21-19
-
-
Reserved
18, 17
R/W
LBK1, LBK0
Loopback Test: There will be no packet on the TX+/- lines under the
Loopback test condition. The loopback function must be independent of
the link state.
00 : normal operation
01 : Reserved
10 : Reserved
11 : Loopback mode
16
R/W
CRC
Append CRC: Setting to 1 means that there is no CRC appended at the
end of a packet. Setting to 0 means that there is CRC appended at the end
of a packet.
15-11
-
-
Reserved


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