RTL8100B(L)
2001-11-9
Rev.1.41
14
5.3 ERSR: Early Rx Status Register
(Offset 0036h, R)
Bit
R/W
Symbol
Description
7-4
-
-
Reserved
3
R
ERGood
Early Rx Good packet: This bit is set whenever a packet is completely
received and the packet is good. Writing a 1 to this bit will clear it.
2
R
ERBad
Early Rx Bad packet: This bit is set whenever a packet is completely
received and the packet is bad. Writing a 1 to this bit will clear it.
1
R
EROVW
Early Rx OverWrite: This bit is set when the RTL8100B(L)'s local
address pointer is equal to CAPR. In the early mode, this is different
from buffer overflow. It happens that the RTL8100B(L) detected an Rx
error and wanted to fill another packet data from the beginning address
of that error packet. Writing a 1 to this bit will clear it.
0
R
EROK
Early Rx OK: The power-on value is 0. It is set when the Rx byte count
of the arriving packet exceeds the Rx threshold. After the whole packet
is received, the RTL8100B(L) will set ROK or RER in ISR and clear
this bit simultaneously. Setting this bit will invoke a ROK interrupt.
5.4 Command Register
(Offset 0037h, R/W)
This register is used for issuing commands to the RTL8100B(L). These commands are issued by setting the corresponding bits for the
function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here.
Bit
R/W
Symbol
Description
7-5
-
-
Reserved
4
R/W
RST
Reset: Setting to 1 forces the RTL8100B(L) to a software reset state
which disables the transmitter and receiver, reinitializes the FIFOs,
resets the system buffer pointer to the initial value (Tx buffer is at
TSAD0, Rx buffer is empty). The values of IDR0-5 and MAR0-7 and
PCI configuration space will have no changes. This bit is 1 during the
reset operation, and is cleared to 0 by the RTL8100B(L) when the reset
operation is complete.
3
R/W
RE
Receiver Enable: When set to 1, and the receive state machine is idle,
the receive machine becomes active. This bit will read back as a 1
whenever the receive state machine is active. After initial power-up,
software must insure that the receiver has completely reset before
setting this bit. This bit will be reset after PCI reset deassertion.
2
R/W
TE
Transmitter Enable: When set to 1, and the transmit state machine is
idle, then the transmit state machine becomes active. This bit will read
back as a 1 whenever the transmit state machine is active. After initial
power-up, software must insure that the transmitter has completely reset
before setting this bit. This bit will be reset after PCI reset deassertion.
1
-
-
Reserved
0
R
BUFE
Buffer Empty: Rx Buffer Empty. There is no packet stored in the Rx
buffer ring.
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