RTL8100B(L)
2001-11-9
Rev.1.41
11
0052h
R/W
CONFIG1
Configuration Register 1
0053H
-
-
Reserved
0054h-0057h
R /W
TimerInt
Timer Interrupt Register: Once having written a nonzero value to
this register, the Timeout bit of the ISR register will be set whenever
the TCTR reaches to this value. The Timeout bit will never be set as
long as the TimerInt register is zero.
0058h
R/W
MSR
Media Status Register
0059h
R/W
CONFIG3
Configuration register 3
005Ah
R/W
CONFIG4
Configuration register 4
005Bh
-
-
Reserved
005Ch-005Dh
R/W
MULINT
Multiple Interrupt Select
005Eh
R
RERID
PCI Revision ID = 10h.
005Fh
-
-
Reserved
0060h-0061h
R
TSAD
Transmit Status of All Descriptors
0062h-0063h
R/W
BMCR
Basic Mode Control Register
0064h-0065h
R
BMSR
Basic Mode Status Register
0066h-0067h
R/W
ANAR
Auto-Negotiation Advertisement Register
0068h-0069h
R
ANLPAR
Auto-Negotiation Link Partner Register
006Ah-006Bh
R
ANER
Auto-Negotiation Expansion Register
006Ch-006Dh
R
DIS
Disconnect Counter
006Eh-006Fh
R
FCSC
False Carrier Sense Counter
0070h-0071h
R/W
NWAYTR
N-way Test Register
0072h-0073h
R
REC
RX_ER Counter
0074h-0075h
R/W
CSCR
CS Configuration Register
0076-0077h
-
-
Reserved
0078h-007Bh
R/W
PHY1_PARM
PHY parameter 1
007Ch-007Fh
R/W
TW_PARM
Twister parameter
0080h
R/W
PHY2_PARM
PHY parameter 2
0081-0083h
-
-
Reserved
0084h
R/W
CRC0
Power Management CRC register0 for wakeup frame0
0085h
R/W
CRC1
Power Management CRC register1 for wakeup frame1
0086h
R/W
CRC2
Power Management CRC register2 for wakeup frame2
0087h
R/W
CRC3
Power Management CRC register3 for wakeup frame3
0088h
R/W
CRC4
Power Management CRC register4 for wakeup frame4
0089h
R/W
CRC5
Power Management CRC register5 for wakeup frame5
008Ah
R/W
CRC6
Power Management CRC register6 for wakeup frame6
008Bh
R/W
CRC7
Power Management CRC register7 for wakeup frame7
008Ch–0093h
R/W
Wakeup0
Power Management wakeup frame0 (64bit)
0094h–009Bh
R/W
Wakeup1
Power Management wakeup frame1 (64bit)
009Ch–00A3h
R/W
Wakeup2
Power Management wakeup frame2 (64bit)
00A4h–00ABh
R/W
Wakeup3
Power Management wakeup frame3 (64bit)
00ACh–00B3h
R/W
Wakeup4
Power Management wakeup frame4 (64bit)
00B4h–00BBh
R/W
Wakeup5
Power Management wakeup frame5 (64bit)
00BCh–00C3h
R/W
Wakeup6
Power Management wakeup frame6 (64bit)
00C4h–00CBh
R/W
Wakeup7
Power Management wakeup frame7 (64bit)
00CCh
R/W
LSBCRC0
LSB of the mask byte of wakeup frame0 within offset 12 to 75
00CDh
R/W
LSBCRC1
LSB of the mask byte of wakeup frame1 within offset 12 to 75
00CEh
R/W
LSBCRC2
LSB of the mask byte of wakeup frame2 within offset 12 to 75
00CFh
R/W
LSBCRC3
LSB of the mask byte of wakeup frame3 within offset 12 to 75
00D0h
R/W
LSBCRC4
LSB of the mask byte of wakeup frame4 within offset 12 to 75
00D1h
R/W
LSBCRC5
LSB of the mask byte of wakeup frame5 within offset 12 to 75
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