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HY5DU12422CLTP-X Datasheet(PDF) 9 Page - Hynix Semiconductor |
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HY5DU12422CLTP-X Datasheet(HTML) 9 Page - Hynix Semiconductor |
9 / 31 page Rev. 1.0 / Mar. 2005 9 1 HY5DU12422C(L)TP HY5DU12822C(L)TP HY5DU121622C(L)TP SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 CKEn CS RAS CAS WE ADDR A10/AP BA Extended Mode Register Set1,2 H X LLL L OP code Mode Register Set1,2 H X LLL L OP code Device Deselect1 HX H XXX X No Operation1 LH H H Bank Active1 HXL L H H RA V Read1 HXL H L H CA L V Read with Autoprecharge1,3 H Write1 HXL H L L CA L V Write with Autoprecharge1,4 H Precharge All Banks1,5 HXL L H L X HX Precharge selected Bank1 LV Read Burst Stop1 HXL H H L X Auto Refresh1 HHLLL H X Self Refresh1 Entry H L LLL H X Exit LH H XXX LH H H Precharge Power Down Mode1 Entry HL H XXX X LH H H Exit LH H XXX LH H H Active Power Down Mode1 Entry HL H XXX X L VVV Exit L H X Note: 1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Precharge command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. *For more information about Truth Table, refer to “Device Operation” section in Hynix website. ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) |
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