P25Q40H datasheet(49/76 Pages) PUYA

Part #	P25Q40H

Description	Ultra Low Power, 4M/2M/1M/512K-bit Serial Multi I/O Flash Memory

PDF	76 Pages

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Manufacturer	PUYA [Puya Semiconductor Co., Ltd.]

Direct Link	http://www.puyasemi.com/index_en.html

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49 / 76 page

P25Q40H/20H/10H/05H Datasheet

Puya Semiconductor

Page 49 of 76

10.26

Program Security Registers (PRSCUR)

The Program Security Registers command is similar to the Page Program command. It allows from 1 to

512bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have

been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers

command.

The Program Security Registers command seq

uence: CS# goes low → sending PRSCUR instruction

→ sending 24 bit address → sending at least one byte data → CS# goes high.

As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is

initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check

the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program

Security Registers cycle, and is 0 when it is completed.

If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.

Program Security Registers command will be ignored.

Address

A23-16

A15-12

A11-9

A8-0

Security Register #1

00H

0001

000

Byte Address

Security Register #2

00H

0010

000

Byte Address

Security Register #3

00H

0011

000

Byte Address

Figure 10-26 Program Security Registers (PRSCUR) Sequence (Command 42)

Command

0

1

2

3

4

5

6

7

42H

CS#

SCLK

SI

8 9 10

28 29 30 31 32 33 34 35 36 37 38 39

3

2

1

7

23 22 21

24- bit address

6

5

4

3

2

1

0

7

CS#

SCLK

SI

MSB

Data Byte 2

6

5

4

3

2

1

0

MSB

6

5

4

3

2

1

0

6

5

4

3

2

1

0

7

Data Byte 1

Data Byte 3

Data Byte 256

0

MSB

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

7

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