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P25Q40H Datasheet(PDF) 4 Page - Puya Semiconductor Co., Ltd. |
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P25Q40H Datasheet(HTML) 4 Page - Puya Semiconductor Co., Ltd. |
4 / 76 page ![]() P25Q40H/20H/10H/05H Datasheet Puya Semiconductor Page 4 of 76 1 Overview General Single 2.30V to 3.60V supply Industrial Temperature Range -40C to 85C Serial Peripheral Interface (SPI) Compatible: Mode 0 and Mode 3 Single, Dual and Quad IO mode - 4M/2M/1M/512K x 1 bit - 2M/1M/512K/256K x 2 bits - 1M/512K/256K/128K x 4 bits Flexible Architecture for Code and Data Storage - Uniform 256-byte Page Program - Uniform 256-byte Page Erase - Uniform 4K-byte Sector Erase - Uniform 32K/64K-byte Block Erase - Full Chip Erase Hardware Controlled Locking of Protected Sectors by WP Pin One Time Programmable (OTP) Security Register - 3*512-Byte Security Registers With OTP Lock 128 bit unique ID for each device Fast Program and Erase Speed - 2ms Page program time - 8ms Page erase time - 8ms 4K-byte sector erase time - 8ms 32K-byte block erase time - 8ms 64K-byte block erase time JEDEC Standard Manufacturer and Device ID Read Methodology Ultra Low Power Consumption - 0.6uA Deep Power Down current - 9uA Standby current - 2.5mA Active Read current at 33MHz - 3.0mA Active Program or Erase current High Reliability - 100,000 Program / Erase Cycles - 20-year Data Retention Industry Standard Green Package Options - 8-pin SOP8 (150mil/208mil) - 8-land USON8 (3x2x0.55mm), (3x2x0.45mm), (3x4x0.55mm) - 8-land WSON8 (6x5x0.75mm) - 8-pin TSSOP8 - WLCSP - KGD for SiP |
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