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P25Q40H Datasheet(PDF) 11 Page - Puya Semiconductor Co., Ltd. |
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P25Q40H Datasheet(HTML) 11 Page - Puya Semiconductor Co., Ltd. |
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11 / 76 page  P25Q40H/20H/10H/05H Datasheet Puya Semiconductor Page 11 of 76 5.4 AC Characteristics for Program and Erase Table 5-4 AC parameters fro program and erase Sym. Parameter 2.3V to 3.6V Units Min. Typ. Max. TESL(6) Erase Suspend Latency 30 us TPSL(6) Program Suspend Latency 30 us TPRS(4) Latency between Program Resume and next Suspend 0.3 us TERS(5) Latency between Erase Resume and next Suspend 0.3 us tPP Page program time (up to 256 bytes) 2 3 ms tPE Page erase time 8 12 ms tSE Sector erase time 8 12 ms tBE1 Block erase time for 32K bytes 8 12 ms tBE2 Block erase time for 64K bytes 8 12 ms tCE Chip erase time 8 12 ms Note 1. tCH + tCL must be greater than or equal to 1/ Frequency. 2. Typical values given for TA=25°C. Not 100% tested. 3. Only applicable as a constraint for a WRSR instruction. 4. Program operation may be interrupted as often as system request. The minimum timing of tPRS must be observed before issuing the next program suspend command. However, in order for an Program operation to make progress, tPRS ≥ 100us must be included in resume-to-suspend loop(s). Not 100% tested. 5. Erase operation may be interrupted as often as system request. The minimum timing of tERS must be observed before issuing the next erase suspend command. However, in order for an Erase operation to make progress, tERS ≥ 200us must be included in resume-to-suspend loop(s). Notes. Not 100% tested. 6. Latency time is required to complete Erase/Program Suspend operation. 7. The value guaranteed by characterization, not 100% tested in production. Figure 5-4 Serial Input Timing SCLK CS# SI MSB SO High-Z LSB tCHSL tSLCH tDVCH tCHDX tSHCH tCHSH tCHCL tCLCH tSHSL tCLH tCLL |
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