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NT5TU64M8EE Datasheet(PDF) 7 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 7 Page - Nanya Technology Corporation. |
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7 / 96 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 7 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved Ball Descriptions Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must maintain to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during Self-Refresh. CS Input Chip Select: All commands are masked when CS is registered high. CS provides for external rank selection on systems with multiple memory ranks. CS is considered part of the command code. RAS, CAS,WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM (LDM, UDM) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 Device, the function of DM or RDQS/ RDQS is enabled by EMRS command to EMR(1). BA0 – BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. A0 – A13 Input Address Inputs: Provides the row address for Activate commands and the column address and Auto Precharge or Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be precharged, the bank is selected by BA0-BA1. The address inputs also provide the op-code during Mode Register Set commands. DQ Input/output Data Inputs/Output: Bi-directional data bus. |
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