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NT5TU64M8EE Datasheet(PDF) 54 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 54 Page - Nanya Technology Corporation. |
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54 / 96 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 54 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved DC & AC Logic Input Levels DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the cross point of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. In single ended mode, the DQS (and RDQS) signals are internally di sabled and don’t care. Input DC logic level Symbol Parameter Min Max Units VIH(dc) DC input logic high VREF + 0.125 VDDQ + 0.3 V VIL(dc) DC input logic low -0.3 VREF - 0.125 V Input AC logic level Symbol Parameter DDR2-667, DDR2-800 Units Min Max VIH(ac) AC input logic high VREF + 0.200 VDDQ+Vpeak V VIL(ac) AC input logic low VSSQ-Vpeak VREF - 0.200 V NOTE 1 Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot. AC input test conditions Symbol Condition Value Units Notes VREF Input reference voltage 0.5 x VDDQ V 1 VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2,3 NOTE 1 Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. NOTE 2 The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. NOTE 3 AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. |
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