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NT5TU64M8EE Datasheet(PDF) 51 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 51 Page - Nanya Technology Corporation. |
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51 / 96 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 51 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved Clock Enable (CKE) Truth Table for Synchronous Transitions Current State CKE Command (N) RAS, CAS, WE, CS Action (N) Notes Previous Cycle Current Cycle Power-Down L L X Maintain Power-Down 11, 13, 15 L H DESELECT or NOP Power-Down Exit 4, 8, 11, 13 Self Refresh L L X Maintain Self Refresh 11, 15, 16 L H DESELECT or NOP Self Refresh Exit 4, 5, 9, 16 Bank(s) Active H L DESELECT or NOP Active Power-Down Entry 4,8,10,11,13 All Banks Idle H L DESELECT or NOP Precharge Power-Down Entry 4,8,10,11,13 H L AUTOREFRESH Self Refresh Entry 6, 9, 11,13 Any State other than listed above H H Refer to the Command Truth Table 7 Notes: 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. 3. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N). 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 6. Self Refresh mode can only be entered from the All Banks Idle state. 7. Must be a legal command as defined in the Command Truth Table. 8. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. 9. Valid commands for Self Refresh Exit are NOP and DESELCT only. 10. Power-Down and Self Refresh cannot be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. See section 2.8 "Power Down" and section 2.7.2 "Self Refresh Command" for a detailed list of restrictions. 11. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks. 12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 13. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefore limited by the refresh requirements. 14. CKE must be maintained high while the device is in OCD calibration mode. 15. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However DT must be driven high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in MRS(1)). 16. Vref must be maintained during Self Refresh operation |
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