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NT5TU64M8EE Datasheet(PDF) 44 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 44 Page - Nanya Technology Corporation. |
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44 / 96 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 44 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved Self-Refresh Command The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS (1) command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. When the DDR2 SDRAM has entered Self-Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self-Refresh Operation to save power. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self-Refresh operation. Once Self-Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high for the entire Self-Refresh exit period (tXSNR or tXSRD) for proper operation. NOP or DESELECT commands must be registered on each positive clock edge during the Self-Refresh exit interval. Since the ODT function is not supported during Self-Refresh operation, ODT has to be turned off tAOFD before entering Self-Refresh Mode and can be turned on again when the tXSRD timing is satisfied. CK/CK T1 T3 T2 CK/CK may be halted CK/CK must be stable CKE >=tXSRD >= tXSNR Tn Tr Tm T5 T4 tRP* tis tAOFD CMD Self Refresh Entry NOP Non-Read Command Read Command T0 tis tis ODT * Device must be in theing "All banks idle" state to enter Self Refresh mode. * ODT must be turned off prior to entering Self Refresh mode. * tXSRD (>=200 tCK) has to be satisfied for a Read or as Read with Auto-Precharge commend. * tXSNR has to be satisfied for any command execept Read or a Read with Auto-Precharge command, where tXSNR is defined as tRFC + 10ns. * The minium CKE low time is defined by the tCKEmin. timming paramester. * Since CKE is an SSTL input, VREF must maintained during Self-Refresh. |
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