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NT5TU64M8EE Datasheet(PDF) 43 Page - Nanya Technology Corporation.

Part # NT5TU64M8EE
Description  DDR2 512Mb SDRAM
Download  96 Pages
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Manufacturer  NANYA [Nanya Technology Corporation.]
Direct Link  http://www.nanya.com
Logo NANYA - Nanya Technology Corporation.

NT5TU64M8EE Datasheet(HTML) 43 Page - Nanya Technology Corporation.

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DDR2 512Mb SDRAM
NT5TU64M8EE / NT5TU32M16EG
43
Version 1.0
Nanya Technology Corp.©
09/2014
All Rights Reserved
Refresh
SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways: by an
explicit Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing the number of device rows
into the rolling 64 ms interval defined the average refresh interval tREFI, which is a guideline to control for distributed refresh
timing.
Auto-Refresh Command
Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is non persistent, so it must be issued
each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the
address bits ”Don’t Care” during an Auto-Refresh command. The DDR2 SDRAM requires Auto-Refresh cycles at an
average periodic interval of tREFI (maximum).
When
CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Auto-Refresh mode.
All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (tRP) before the Auto-Refresh
Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the
external address bus is required once this cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the
Auto-Refresh Command
and the next Activate Command or subsequent Auto-Refresh Command must be greater than or
equal to the Auto-Refresh cycle time (tRFC).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval
is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the
maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 * tREFI.
T0
T2
T1
T3
AR
CK, CK
CMD
Precharge
> = t
RP
NOP
AUTO
REFRESH
ANY
NOP
> = t
RFC
> = t
RFC
AUTO
REFRESH
NOP
NOP
NOP
CKE
"high"


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