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NT5TU64M8EE Datasheet(PDF) 36 Page - Nanya Technology Corporation.

Part # NT5TU64M8EE
Description  DDR2 512Mb SDRAM
Download  96 Pages
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Manufacturer  NANYA [Nanya Technology Corporation.]
Direct Link  http://www.nanya.com
Logo NANYA - Nanya Technology Corporation.

NT5TU64M8EE Datasheet(HTML) 36 Page - Nanya Technology Corporation.

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DDR2 512Mb SDRAM
NT5TU64M8EE / NT5TU32M16EG
36
Version 1.0
Nanya Technology Corp.©
09/2014
All Rights Reserved
Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks
NOP
NOP
NOP
READ A
T0
T2
T1
T3
T4
T5
T6
T7
T8
CMD
DQ
BR-P404(8)
NOP
AL + BL/2 clks + 1
Dout A0
Dout A1
Dout A2
Dout A3
CL = 4
RL = 4
>=tRAS
>=tRP
DQS,
DQS
NOP
>=tRTP
Dout A4
Dout A5
Dout A6
Dout A7
Precharge
NOP
Bank A
Activate
first 4-bit prefetch
second 4-bit prefetch
CK, CK
Burst Write followed by Precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay
must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued.
This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the
Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does
not support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table
in this datasheet) and is not the programmed value for tWR in the MRS.
Examples:
Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3
NOP
NOP
NOP
NOP
NOP
WRITE A
Post CAS
T
0
T
2
T
1
T
3
T
4
T
5
T
6
T
7
T
8
WL = 3
BW-P3
CMD
DQ
NOP
DIN
A0
DIN
A1
DIN
A2
DIN
A3
>=tWR
Completion of
the Burst Write
Precharge
A
NOP
DQS,
DQS
CK, CK


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