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NT5TU64M8EE Datasheet(PDF) 31 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 31 Page - Nanya Technology Corporation. |
31 / 96 page DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 31 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved Burst Interruption Interruption of a read or write burst is only allowed on burst of 8. Burst interrupt of 4 is prohibited. Below are the constraints of burst interruption: 1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or Precharge Command is prohibited. 2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or Precharge Command is prohibited. 3. Read burst interrupt occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohibited. 4. Write burst interrupt occur exactly two clocks after the previous Write command. Any other Read burst interrupt timings are prohibited. 3. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM. 4. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted. 5. Read burst interruption is allowed by a Read with Auto-Precharge command. 6. Write burst interruption is allowed by a Write with Auto-Precharge command. Notes: 1. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end. |
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