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NT5TU64M8EE Datasheet(PDF) 25 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 25 Page - Nanya Technology Corporation. |
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25 / 96 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 25 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS (1)) Basic Burst Read Timing DQS, DQS DQ DQS DQS t RPRE t DQSQmax tRPST t DQSCK tAC Dout Dout Dout Dout CLK, CLK CLK CLK t CH tCL t CK DO-Read t QH DQSQmax t QH t t LZ t HZ Examples: Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4) NOP NOP NOP NOP NOP NOP NOP READ A T0 T2 T1 T3 T4 T5 T6 T7 T8 Dout A0 Dout A1 Dout A2 Dout A3 RL = 5 AL = 2 CL = 3 NOP <= tDQSCK CMD DQ BRead523 DQS, DQS Post CAS CK, CK |
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