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NT5TU64M8EE Datasheet(PDF) 19 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 19 Page - Nanya Technology Corporation. |
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19 / 96 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 19 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved ODT related timings MRS command to ODT update delay During normal operation the value of the effective termination resistance can be changed with an EMRS command. The update of the Rtt setting is done between tMOD, min and tMOD, max, and CKE must remain HIGH for the entire duration of tMOD window for proper operation. The timings are shown in the following timing diagram. CKE Rtt CK, CK tIS CMD tAOFD EMRS NOP NOP NOP NOP NOP tMOD, min tMOD, max Old setting Updating New setting EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal) Setting in this diagram is the Register and I/O setting, not what is measured from outside. However, to prevent any impedance glitch on the channel, the following conditions must be met. - tAOFD must be met before issuing the EMRS command. - ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met. Now the ODT is ready for normal operation with the new setting, and the ODT may be raised again to turn on the ODT. Following timing diagram shows the proper Rtt update procedure. CKE Rtt CK, CK tIS CMD tAOFD EMRS NOP NOP NOP NOP tMOD, max Old setting New setting EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal) Setting in this diagram is the Register and I/O setting, not what is measured from outside. tAOND NOP |
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