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NT5TU64M8EE Datasheet(PDF) 17 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 17 Page - Nanya Technology Corporation. |
17 / 96 page ![]() DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 17 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved Extended Mode Register Set EMRS (2) The Extended Mode Registers (2) controls refresh related features. The default value of the extended mode register(2) is not defined, therefore the extended mode register(2) is written by asserting low on CS, RAS, CAS, WE, BA0, high on BA1, while controlling the states of address pin A0-A13. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. Extended Mode Register Set -EMRS (3) Programming All bits in EMRS(3) expect BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode register during initialization. BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 1 1 0 |
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