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NT5TU64M8EE Datasheet(PDF) 13 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 13 Page - Nanya Technology Corporation. |
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13 / 96 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 13 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved Mode Register – MR Programming BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 0 PPD DLL TM BT A12 A8 A3 0 0 0 1 1 1 BA1 BA0 A7 0 0 0 0 1 1 A2 A1 A0 BL 1 0 0 1 0 4 1 1 0 1 1 8 A11 A10 A9 A6 A5 A4 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 8 7 5 4 6 5 7 6 2 Reserved 3 Reserved 4 3 EMRS(2) EMRS(3) WR CAS Latency Reserved Reserved MR select mode MR Normal EMRS(1) Test Fast exit (tXARD) No Sequential Slow exit (tXARDS) Yes Interleave MR select WR CAS latency Burst Length PPD DLL Reset Burst Type NOTE 1 Bits of Reserved for future use must be set to 0 when programming the MR. NOTE 2 For DDR2-400/533, WR (write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR[cycles] = RU{ tWR[ns] / tCK[ns] }, where RU stands for round up). For DDR2-667/800, WR min is determined by tCK(avg) max and WR max is determined by tCK(avg) min. WR[cycles] = RU{ tWR[ns] / tCK(avg)[ns] }, where RU stands for round up. The mode register must be programmed to this value. This is also used with tRP to determine tDAL. |
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