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NT5TU64M8EE Datasheet(PDF) 10 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 10 Page - Nanya Technology Corporation. |
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10 / 96 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 10 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved Power-up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for POWER UP and Initialization. 1. Either one of the following sequence is required for Power-up. (1) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state (all other inputs may be undefined) The VDD voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min; and during the VDD voltage ramp up, IVDD-VDDQI≦0.3 volts. Once the ramping of the supply voltages is complete (when VDDQ crosses VDDQ min), the supply voltage specifications in Re-commanded DC operating conditions table. - VDD, VDDL, and VDDQ are driven from a signal power converter output, AND - VTT is limited to 0.95V max, AND - Vref tracks VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time. - VDDQ>=VREF must be met at all times. (2) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state, all other inputs may be undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up. During the ramping of the supply voltages, VDD≧VDDL≧VDDQ must be maintained and is applicable to both AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the ramping of the supply voltages is complete, the supply voltage specifications provided in Re-commanded DC operating conditions table. - Apply VDD/VDDL before or at the same time as VDDQ. - VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDDmin. - Apply VDDQ before or at the same time as VTT. - The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.) - Vref must track VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time. - VDDQ ≧ VREF must be met at all time. - Apply VTT. 2. Start clock (CK, CK) and maintain stable condition. |
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