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NT5TU64M8EE Datasheet(PDF) 91 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 91 Page - Nanya Technology Corporation. |
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91 / 96 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 91 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved Specific Note 35 Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply. The jitter specified is a random jitter meeting a Gaussian distribution. Input clock jitter spec parameter apply Parameter Symbol DDR2-800 DDR2-667 Units min max min max Clock period jitter tJIT(per) -100 100 -125 125 ps Clock period jitter during DLL locking period tJIT(per,lck) -80 80 -100 100 ps Cycle to cycle clock period jitter tJIT(cc) -200 200 -250 250 ps Cycle to cycle clock period jitter during DLL locking period tJIT(cc,lck) -160 160 -200 200 ps Cumulative error across 2 cycles tERR(2per) -150 150 -175 175 ps Cumulative error across 3 cycles tERR(3per) -175 175 -225 225 ps Cumulative error across 4 cycles tERR(4per) -200 200 -250 250 ps Cumulative error across 5 cycles tERR(5per) -200 200 -250 250 ps Cumulative error across n cycles,n = 6 ... 10, inclusive tERR(6-10per) -300 300 -350 350 ps Cumulative error across n cycles,n = 11 ... 50, inclusive tERR(11-50per) -450 450 -450 450 ps Duty cycle jitter tJIT(duty) -100 100 -125 125 ps Definitions: - tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. - tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses. |
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