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NT5TU64M8EE Datasheet(PDF) 70 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 70 Page - Nanya Technology Corporation. |
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70 / 96 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 70 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved General notes, which may apply for all AC parameters General Note 1 DDR2 SDRAM AC timing reference load The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. This reference load is also used for output slew rate characterization. The output timing reference voltage level for single ended signals is the cross point with VTT. The output timing reference voltage level for differential signals is the cross point of the true (e.g. DQS) and the complement (e.g. DQS) signal. General Note 2 Slew Rate Measurement Levels a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b) Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges and from Vref(dc) to VIL(ac),max for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = + 500 mV (+ 250 mV to - 500 mV for falling edges). c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. General Note 3 DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as following |
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