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NT5TU64M8EE Datasheet(PDF) 66 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 66 Page - Nanya Technology Corporation. |
66 / 96 page DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 66 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved AC & DC operating conditions Timing parameters (DDR2-800) Parameter Symbol DDR2-800 Units 34 Notes Min Max Clock cycle time tCK 2500 8000 ps 35,36 CK HIGH pulse width tCH 0.48 0.52 tCK(avg) 35,36 CK LOW pulse width tCL 0.48 0.52 tCK(avg) 35,36 Write command to DQS associated clock edge WL RL - 1 DQS latching rising transitions to associated clock edges tDQSS - 0.25 0.25 tCK(avg) 30 DQS falling edge to CK setup time tDSS 0.2 - tCK(avg) 30 DQS falling edge hold time from CK tDSH 0.2 - tCK(avg) 30 DQS input HIGH pulse width tDQSH 0.35 - tCK(avg) DQS input LOW pulse width tDQSL 0.35 - tCK(avg) Write preamble tWPRE 0.35 - tCK(avg) Write postamble tWPST 0.4 0.6 tCK(avg) 10 Address and control input setup time tIS(base) 175 - ps 5,7,9,22 ,29 Address and control input hold time tIH(base) 250 - ps 5,7,9,23 ,29 Control & Address input pulse width for each input tIPW 0.6 - tCK(avg) DQ and DM input setup time (differential strobe) tDS(base) 50 - ps 6,7,8,20 ,28,31 DQ and DM input hold time (differential strobe) tDH(base) 125 - ps 6,7,8,21 ,28,31 DQ and DM input pulse width for each input tDIPW 0.35 - tCK(avg) DQ output access time from CK, CK tAC - 400 400 ps 40 DQS output access time from CK, CK tDQSCK - 350 350 ps 40 Data-out high-impedance time from CK, CK tHZ - tAC,max ps 18,40 DQS(/DQS) low-impedance time from CK, CK tLZ(DQS) tAC,min tAC,max ps 18,40 DQ low-impedance time from CK, CK tLZ(DQ) 2 x tAC,min tAC,max ps 18,40 DQS-DQ skew for DQS and associated DQ signals tDQSQ - 200 ps 13 CK half pulse width tHP Min(tCH(abs),tCL(abs) ) - ps 37 DQ hold skew factor tQHS - 300 ps 38 DQ/DQS output hold time from DQS tQH tHP-tQHS - ps 39 Read preamble tRPRE 0.9 1.1 tCK(avg) 19,41 |
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