NT5TU64M8EE datasheet(62/96 Pages) NANYA

Part #	NT5TU64M8EE

Description	DDR2 512Mb SDRAM

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Manufacturer	NANYA [Nanya Technology Corporation.]

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DDR2 512Mb SDRAM

NT5TU64M8EE / NT5TU32M16EG

62

Version 1.0

Nanya Technology Corp.©

09/2014

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD6

Self refresh current;

CK and

CK at 0 V;

CKE ≤ 0.2 V;

Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING

IDD7

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD);

tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD),

tRCD = 1 x tCK(IDD);

CKE is HIGH,

CS is HIGH between valid commands;

Address bus inputs are STABLE during DESELECTs;

Data pattern is same as IDD4R;

- Refer to the following pages for detailed timing conditions

Notes:

1.

IDD specifications are tested after the device is properly initialized

2.

Input slew rate is specified by AC Parametric Test Condition

3.

IDD parameters are specified with ODT disabled.

4.

Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with

all combinations of EMRS bits 10 and 11.

5.

For DDR2-667/800 testing, tCK in the Conditions should be interpreted as tCK(avg)

6.

Definitions for IDD

- LOW = Vin ≤ VILAC(max)

- HIGH = Vin ≥ VIHAC(min)

- STABLE = inputs stable at a HIGH or LOW level

- FLOATING = inputs at VREF = VDDQ/2

- SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and

control signals, and inputs changing between

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NT5TU64M8EE Datasheet(PDF) 62 Page - Nanya Technology Corporation.

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