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NT5TU64M8EE Datasheet(PDF) 59 Page - Nanya Technology Corporation. |
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NT5TU64M8EE Datasheet(HTML) 59 Page - Nanya Technology Corporation. |
59 / 96 page DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 59 Version 1.0 Nanya Technology Corp.© 09/2014 All Rights Reserved OCD default characteristics Description Parameter Min Nom Max Units Notes Output slew rate Sout 1.5 - 5 V/ns 1-6 NOTE 1 Absolute Specifications (TOPER; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for timing, voltage, and slew rate are no longer applicable if OCD is changed from default settings. NOTE 2 Slew rate measured from vil(ac) to vih(ac). NOTE 3 The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. NOTE 4 DRAM output slew rate specification applies to 400 MT/s, 533 MT/s & 667 MT/s speed bins. NOTE 5 Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS specification. NOTE 5 DDR2 SDRAM output slew rate test load is defined in the AC Timing specification Table. |
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