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FP6711 Datasheet(PDF) 12 Page - Fitipower Integrated Technology Inc. |
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FP6711 Datasheet(HTML) 12 Page - Fitipower Integrated Technology Inc. |
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12 / 13 page  12 FP6711-1.4-DEC-2011 FP6711 85T fitipower integrated technology lnc. Application Information (Continued) (5) Compensation of the Control Loop An R/C network must be connected to the COMP pin in order to stabilize the control loop of the converter. Both the pole generated by the inductor L1 and the zero caused by the ESR and capacitance of the output capacitor must be compensated. The network shown in Figure 24 satisfies these requirements. VOUT ERROR AMP 8 CC Rc 9 R4 R3 0.5V Figure 24. Compensation of Control Loop Resistor RC and capacitor CC depend on the chosen inductance. The equation for the loop dynamics is shown as below : fZER01 = HZ 2 x π x CC 1 x Rc The FP6711 uses current mode control with internal adaptive slope compensation. Current mode control eliminates the 2 nd order filter due to the inductor and output capacitor exhibited in voltage mode controllers and simplifies it to a single-pole filter response. Thermal Information The maximum junction temperature (TJ) of the FP6711 devices is recommended to 125°C. The thermal resistance of the 10-pin MSOP package is JA=160°C/W. Specified regulator operations are assured to a maximum ambient temperature (TA) of 70°C. Therefore, the maximum power dissipation is about 340mW. More power can be dissipated if the maximum ambient temperature of the application is lower. mW 40 3 C/W 160 C 70 - C 125 T - T P JA A J(MAX) D(MAX) Layout Considerations As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path as indicated in bold in Figure 25. The input capacitor, output capacitor and the inductor should be placed as close to the IC as possible. Use a common ground node as shown in Figure 25 to minimize the effects of ground noise. The compensation circuit and the feedback divider should be placed as close to the IC as possible. To layout the control ground, it is recommended to use short traces as well, separated from the power ground traces. Connect both grounds close to the ground pin of the IC as indicated in the layout diagram in Figure25. This avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current. C4 OUTPUT ADEN LBI VBAT FP6711 EN COMP FB LBO VOUT GND SW R1 R2 L1 R5 C1 CC RC R3 R4 Battery LBO Figure 25. Layout Diagram |
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Similar Description - FP6711 |
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