Integrated Silicon Solution, Inc. — 1-800-379-4774

1

SR020-1O

05/24/99

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which

may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.

FEATURES

• High-speed access time: 10, 12, 15, 20, 25 ns

• Low active power: 400 mW (typical)

• Low standby power

— 250

µW (typical) CMOS standby

— 55 mW (typical) TTL standby

• Fully static operation: no clock or refresh

required

• TTL compatible inputs and outputs

• Single 5V power supply

DESCRIPTION

The

32,768 word by 8-bit static RAMs. They are fabricated using

able process coupled with innovative circuit design tech-

niques, yields access times as fast as 10 ns maximum.

When

CE is HIGH (deselected), the device assumes a standby

mode at which the power dissipation can be reduced down to

250

µW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW

Chip Enable (

CE) input and an active LOW Output Enable (OE)

input. The active LOW Write Enable (

WE) controls both writing

and reading of the memory.

The IS61C256AH is pin compatible with other 32K x 8 SRAMs

and are available in 28-pin PDIP, SOJ, and TSOP (Type I)

packages.

IS61C256AH

32K x 8 HIGH-SPEED CMOS STATIC RAM

MAY 1999

FUNCTIONAL BLOCK DIAGRAM

A0-A14

CE

OE

WE

32K X 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7