6

Integrated Silicon Solution, Inc. — 1-800-379-4774

SR020-1O

05/24/99

IS61C256AH

-10

-12

-15

-20

-25

Symbol Parameter

Min.

Max

Min. Max.

Min. Max.

Min. Max.

Min. Max.

Unit

Write Cycle Time

10

—

12

—

15

—

20

—

25

—

ns

CE to Write End

9

—

10

—

10

—

13

—

15

—

ns

Address Setup Time

9

—

10

—

12

—

15

—

20

—

ns

to Write End

Address Hold

0

—

0

—

0

—

0

—

0

—

ns

from Write End

Address Setup Time

0

—

0

—

0

—

0

—

0

—

ns

WE Pulse Width (OE LOW)

8

—

8

—

10

—

13

—

15

—

ns

WE Pulse Width (OE HIGH)

6.5

—

7

—

8

—

10

—

12

—

ns

Data Setup to Write End

7

—

7

—

9

—

10

—

12

—

ns

Data Hold from Write End

0

—

0

—

0

—

0

—

0

—

ns

WE LOW to High-Z Output

—

6

—

6

—

7

—

8

—

10

ns

WE HIGH to Low-Z Output

0

—

0

—

0

—

0

—

0

—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured

±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the write.

AC WAVEFORMS

WRITE CYCLE NO. 1 (

WE

WE

WE

WE

DATA UNDEFINED

VALID ADDRESS

HIGH-Z

ADDRESS

CE

WE

CE_WR1.eps