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ALC5611-GR Datasheet(PDF) 17 Page - Realtek Semiconductor Corp. |
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ALC5611-GR Datasheet(HTML) 17 Page - Realtek Semiconductor Corp. |
17 / 73 page ![]() ALC5611 Datasheet AC’97 Audio Codec + Touch Panel Controller 9 Track ID: JATR-1076-21 Rev. 1.1 7.3. Clocking The Stereo_SYSCLK can be selected from MCLK or PLL. This means MCLK is always provided externally, and the driver should arrange the clock of each block and setup each divider. 7.3.1. Phase-Locked Loop A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. Typical choices are 2.048MHz, 4.096MHz, and 13MHz. The source of the PLL can be set to MCLK or MCLK/2 by setting PLL_pre_div. The ALC5611 SYSCLK frequency is 24.576MHz. If the system cannot provide 24.576MHz to the ALC5611, the PLL of the ALC5611 can be used to generate a frequency near 24.576MHz. As the PLL parameter is configured through the AC link, the input clock to the MCLK pin must be between 2.048MHz and 80MHz. After the AC link is connected, the driver must configure the PLL in order to output a frequency close to the SYSCLK (24.576MHz). The accuracy of audio output frequency will depend on the accuracy of PLL output. The PLL transmit formula is: FOUT = (MCLK * (N+2))/((M+2) * (K+2)) {Typical K=2} Table 8. AC-Link Clock Setting Table (Unit: MHz) MCLK N M FVCO K FOUT 13 66 7 98.222 2 24.555 3.6864 78 1 98.304 2 24.576 2.048 94 0 98.304 2 24.576 4.096 70 1 98.304 2 24.576 After a Cold Reset, PLL related Registers are reset to default values, however, they are not reset to default values after a soft-reset (write Reg00). Firmware should not power down the PLL when the PLL output is used as Stereo_SYSCLK. Note: The ALC5611 will only be enabled after an AC-Link Warm Reset. 7.3.2. AC’97 Mode For the AC-Link controller, the BIT_CLK driven by PLL will only be enabled after a warm reset. The sampling rate of the stereo ADC and stereo DAC can be configured separately and is controlled by Reg2C (stereo DAC) and Reg32 (stereo ADC). |
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