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ALC5611-GR Datasheet(PDF) 68 Page - Realtek Semiconductor Corp. |
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ALC5611-GR Datasheet(HTML) 68 Page - Realtek Semiconductor Corp. |
68 / 73 page ALC5611 Datasheet AC’97 Audio Codec + Touch Panel Controller 60 Track ID: JATR-1076-21 Rev. 1.1 9.3.3. AC-Link Clocks Table 86. AC-Link Clock Parameters Parameter Symbol Min Typ Max Units BIT_CLK Frequency - - 12.288 - MHz BIT_CLK Period Tclk_period - 81.4 - ns BIT_CLK Output Jitter - - - 750 ps BIT_CLK High Pulse Width (Note 2) Tclk_high 36 40.7 45 ns BIT_CLK Low Pulse Width (Note 2) Tclk_low 36 40.7 45 ns SYNC Frequency - - 48.0 - kHz SYNC Period Tsync_period - 20.8 - µs SYNC High Pulse Width Tsync_high - 1.3 - µs SYNC Low Pulse Width Tsync_low - 19.5 - µs Note: Worse case duty cycle restricted to 45/55. 9.3.4. AC-Link Data Output and Input Timing Figure 16. Data Output and Input Timing Table 87. AC-Link Data Timing Parameters Parameter Symbol Min Typ Max Units Output Valid Delay from Rising Edge of BIT_CLK tco - - 15 ns Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output. Note 2: 50pF external load Parameter Symbol Min Typ Max Units Input Setup to Falling Edge of BIT_CLK tsetup 10 - - ns Input Hold from Falling Edge of BIT_CLK thold 10 - - ns Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output. Parameter Symbol Min Typ Max Units BIT_CLK Combined Rise or Fall Plus Flight Time - - - 7 ns SDATA Combined Rise or Fall Plus Flight Time - - - 7 ns Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes. |
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