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ALC5611-GR Datasheet(PDF) 43 Page - Realtek Semiconductor Corp. |
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ALC5611-GR Datasheet(HTML) 43 Page - Realtek Semiconductor Corp. |
43 / 73 page ![]() ALC5611 Datasheet AC’97 Audio Codec + Touch Panel Controller 35 Track ID: JATR-1076-21 Rev. 1.1 8.21. Reg-42h: General Purpose Control Register 2 Default: 0000h Table 33. Reg-42h: General Purpose Control Register 2 Name Bits Read/Write Reset State Description Reserved 15:14 RW 0’h Reserved se_btl_clsab 13 RW 0’b Single End & BTL of SPK_Class AB Selection 0: Differential Mode 1: Single-End Mode Reserved 12:1 RW 0’h Reserved pll_pre_div 0 RW 0’b PLL Pre-Divider 0b: ÷1 1b: ÷2 8.22. Reg-44h: PLL Control Default: 0000h Table 34. Reg-44h: PLL Control Name Bits Read/Write Reset State Description pll_n_code 15:8 RW 00’h N[7:0] Code for Analog PLL 00000000: Div 2 00000001: Div 3 ……….. 11111111: Div 257 pll_m_bypass 7 RW 0’h Bypass PLL M 0b: No bypass 1b: Bypass pll_k_code 6:4 RW 0’h K[2:0] Code for Analog PLL 000: Div 2 001: Div 3 ………… 111: Div 9 pll_m_code 3:0 RW 0’h M[3:0] Code for Analog PLL 0000: Div 2 0001: Div 3 ………… 1111: Div 17 Note: The PLL transmit formula is FOUT = (MCLK * (N+2))/((M+2) * (K+2)) {Typical K=2} |
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