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ALC5610-GR Datasheet(PDF) 21 Page - Realtek Semiconductor Corp. |
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ALC5610-GR Datasheet(HTML) 21 Page - Realtek Semiconductor Corp. |
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21 / 93 page  ALC5610 Datasheet AC’97 Audio Codec + Touch Panel Controller + Voice PCM Interface 12 Track ID: JATR-1076-21 Rev. 1.4 7.3.2. AC’97 Mode For the AC-Link controller, the BIT_CLK driven by PLL will only be enabled after a warm reset. The sampling rate of the stereo ADC and stereo DAC can be configured separately and is controlled by Reg2C (stereo DAC) and Reg32 (stereo ADC). 7.3.3. Voice_I2S/PCM Interface The ALC5610 supports an independent digital interface for Voice Audio. The voice audio digital interface is used to input digital data to the voice DAC, or output digital data from the voice ADC. The Voice Audio Digital Interface can be configured to Master mode or Slave mode. Whether in Master mode or Slave mode, the sample rate of the Voice ADC and Voice DAC is set via Reg64 and Reg66. In Master mode, the main clock of the Voice_I2S/PCM interface can be input selected from MCLK (with or without a PLL) or EXTCLK. VBCLK and VSLRCK will be configured as output. DRIVER has to set each divider (Reg64 & Reg66) to arrange the clock distribution. See section 12 Appendix A: Voice PCM Interface, page 81 for details. In Slave mode, the main clock of the Voice_I2S/PCM can be input from MCLK or EXTCLK. VBCLK is synchronized externally. VBCLK and VSLRCK will be configured as input. The driver has to set each divider (Reg64 and Reg66) to arrange the clock distribution (see section 12.2 Slave Mode: (voice_port_sel=1), page 83, for more information. If VBCLK provides 64Fs, 128Fs, or 256Fs externally, the ACL5610 can use VBCLK input as the main clock of the Voice_I2S/PCM. See section 12 Appendix A: Voice PCM Interface, page 81 for details. 7.3.4. Voice ADC The ALC5610 supports Voice ADC for transmitting voice data to a Bluetooth device. The Voice ADC is implemented by sharing from the Right Channel of the Stereo ADC (by setting voice_adc_enable). When voice_adc_enable=0, the L/R channel stereo ADC sample rate is set according to the stereo sample rate (ADC_SAMPLE_RATE) and output to slots 3 & 4 of the AC’97 interface. When voice_adc_enable=1, the sample rate of the Left channel is set by the stereo sample rate (ADC_SAMPLE_RATE). The sample rate of the Right channel is set by the voice sample rate (Reg64 & Reg66). The Left channel ADC data is output to the Left (slot 3) and duplicated to the Right (slot 4) of the AC’97 interface. The Right channel of the Stereo ADC data is then used as a Voice ADC and output to voice_I2S/PCM. |
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