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ALC5610-GR Datasheet(PDF) 9 Page - Realtek Semiconductor Corp. |
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ALC5610-GR Datasheet(HTML) 9 Page - Realtek Semiconductor Corp. |
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9 / 93 page  ALC5610 Datasheet AC’97 Audio Codec + Touch Panel Controller + Voice PCM Interface ix Track ID: JATR-1076-21 Rev. 1.4 List of Figures FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................4 FIGURE 2. AUDIO MIXER PATH....................................................................................................................................................5 FIGURE 3. PIN ASSIGNMENTS ......................................................................................................................................................6 FIGURE 4. AC-LINK WAKE UP TIMING......................................................................................................................................13 FIGURE 5. DEFAULT ALC5610 SLOT ARRANGEMENT – CODEC ID ALWAYS 00 .......................................................................14 FIGURE 6. CONTROLLER AND CODEC CONNECTION ..................................................................................................................14 FIGURE 7. PCM MONO DATA MODE A FORMAT (BCLK_POLARITY=0).....................................................................................15 FIGURE 8. PCM MONO DATA MODE A FORMAT (BCLK_POLARITY=1).....................................................................................15 FIGURE 9. PCM MONO DATA MODE B FORMAT (BCLK_POLARITY=0) ....................................................................................16 FIGURE 10. PCM STEREO DATA MODE A FORMAT (BCLK_POLARITY=0)....................................................................................16 FIGURE 11. PCM STEREO DATA MODE B FORMAT (BCLK_POLARITY=0)....................................................................................16 FIGURE 12. I2S DATA FORMAT (BCLK_POLARITY=0)...................................................................................................................17 FIGURE 13. LEFT-JUSTIFIED DATA FORMAT (BCLK_POLARITY=0)...............................................................................................17 FIGURE 14. RIGHT-JUSTIFIED DATA FORMAT (BCLK_POLARITY=0).............................................................................................17 FIGURE 15. I2S SIGNAL LINK SLAVE MODE DIAGRAM (ALC5610 IS SLAVE) ..............................................................................18 FIGURE 16. I2S SIGNAL LINK MASTER MODE DIAGRAM (ALC5610 IS MASTER) .......................................................................18 FIGURE 17. 4-WIRE RESISTIVE TOUCH PANEL CIRCUIT ..............................................................................................................26 FIGURE 18. AUTO VOLUME CONTROL BLOCK DIAGRAM............................................................................................................27 FIGURE 19. EXAMPLE OF ALC5610 POWER-DOWN/POWER-UP FLOW .......................................................................................29 FIGURE 20. GPIO IMPLEMENTATION...........................................................................................................................................30 FIGURE 21. POWER CONTROL TO MIC INPUT .............................................................................................................................44 FIGURE 22. GPIO AND IRQ LOGIC .............................................................................................................................................50 FIGURE 23. JACK-INSERT-DETECT PULL-UP RESISTOR IMPLEMENTED VIA AN EXTERNAL CIRCUIT ............................................53 FIGURE 24. COLD RESET TIMING ................................................................................................................................................72 FIGURE 25. WARM RESET TIMING...............................................................................................................................................72 FIGURE 26. DATA OUTPUT AND INPUT TIMING............................................................................................................................73 FIGURE 27. SIGNAL RISE AND FALL TIMING................................................................................................................................74 FIGURE 28. AC-LINK LOW POWER MODE TIMING......................................................................................................................75 FIGURE 29. I2S/PCM MASTER MODE TIMING.............................................................................................................................76 FIGURE 30. I2S/PCM SLAVE MODE TIMING................................................................................................................................77 |
Similar Part No. - ALC5610-GR |
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Similar Description - ALC5610-GR |
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